
Advanced Clock Drivers Devices
Freescale Semiconductor
16
MPC9894
IEEE STD.1149.1(JTAG)
This section describes the IEEE Std. 1149.1 compliant
Test Access Port (TAP) and Boundary Scan Architecture
implementation in the MPC9894. Special private instructions
are provided to assist in production test control. These
instructions combined with control of the test mode inputs
and the use of shared inputs and outputs provide for full
production test mode access and control.
Test Access Port Interface Signals
Table 29
lists the TAP interface signals and their
descriptions.
Instruction Register
Instructions
Table 31
lists the public instructions provided in the
implementation and their instruction codes. Public
instructions are accessible by the customer for board test and
may also be used for production chip test.
Boundary-Scan Register
A full description of the boundary scan register may be found in the BSDL file.
Device Identification Register (0x0281D01D)
Table 29. TAP Interface Signals
Signal Name
Description
Function
Direction
Active State
TCK
Test Clock
Test logic clock.
Input
—
TMS
Test Mode Select
TAP mode control input.
Input
—
TDI
Test Data In
Serial test instruction/data input.
Input
—
TRST_B
Test Reset Bar
Asynchronous test controller reset.
Input
—
TDO
Test Data Out
Serial test instruction/data output.
Output
—
Table 30. Instruction Register
Bit Position
4
3
2
1
0
Field
IR
Capture-IR Value
0
0
0
0
1
Table 31. TAP Controller Public Instructions
Instruction
Code
Enabled Serial Test Data Path
BYPASS
11111
Bypass Register
CLAMP
01100
Bypass Register
EXTEST
00000
Boundary Scan Register
HIGHZ
01001
Bypass Register
IDCODE
00001
ID Register
SAMPLE
00010
Boundary Scan Register
Table 32. Device Identification Register
Bit
Position
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Field
Version
Part Number
Manufacturer ID
Value
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
1
1
1
0
1