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參數(shù)資料
| 型號： | MPC9894 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Input Redundant IDCS Clock Generator |
| 中文描述： | 四路輸入冗余IDC機房，時鐘發(fā)生器 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 367K |
| 代理商： | MPC9894 |
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Advanced Clock Drivers Devices
Freescale Semiconductor
17
MPC9894
POWER SUPPLY CONFIGURATION
The MPC9894 operates from either a 3.3 V or 2.5 V
voltage supply for the device core. The pin SEL_2P5V is
used to logically indicate the core supply voltage. This
selection is done by setting the pin to a logic 1 for 2.5 V or
logic 0 for 3.3 V operation.
The input and output supply voltage may be set for either
3.3 V or 2.5 V and can be individually set for inputs and banks
of outputs.
Table 33. Power Supply Configuration
lists the
supply pins and what pin or group of pins are associated with
each supply. Note, that for output skew and SPO
specifications to be valid the input, feedback input and output,
and the output bank must all be at the same voltage level.
Power Supply Sequencing and MR Operation
Figure 5
defines the release time and the minimum pulse
length for
MR
pin. The
MR
release time is based upon the
power supply being stable and within V
DD
specifications.
Refer to
Table 39
for actual parameter values. The MPC9894
may be configured after release of reset and the outputs will
be stable for use after lock indication is obtained.
V
DD
must ramp up prior to or concurrent with the other
power supply pins. It is recommended that the maximum slew
rate for the V
DD
supply not exceed 0.5 V/ms.
Power Supply Bypassing
The MPC9894 is a mixed analog/digital product. The
differential architecture of the MPC9894 supports low noise
signal operation at high frequencies. In order to maintain its
superior signal quality, all V
CC
pins should be bypassed by
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
Clock Outputs
The MPC9894 clock outputs are differential LVPECL
voltage compatible. The outputs are designed to drive a
single 50
impedance load that is properly terminated. The
media pin is used to select between either of two output
termination techniques.
Selection of media = 0 sets all of the outputs to drive up to
50
parallel terminated (to V
TT
) transmission lines. With
media = 1 the outputs are designed to drive 50
transmission line terminated with a single 100 differential load
resistor. See
Figure 7
and
Figure 8
for diagrams of each of
these termination techniques. Note, that the traditional output
pulldown resistors for emitter follower biasing are not
required for the MPC9894. If external feedback is used, the
QFB output must be terminated with the same technique as
selected with the media pin. Once a termination technique is
chosen, that technique must be used for all MPC9894
outputs to guarantee output skew timing.
The recommended termination technique is media = 1.
This provides a simpler termination method and also reduces
overall power consumption of the MPC9894. Unused outputs
may be powered-down via the Output Power-Up and
Feedback Power-Up registers to conserve power. If external
feedback is selected the programming of the PWR_QFB bit
is ignored.
Table 33. Power Supply Configuration
Supply Voltage
Description
Value
V
DD
Positive power supply for the device core, output status and control inputs. (3.3 V or 2.5 V)
3.3 V or 2.5 V
V
DDAB
Supply voltage for output banks A and B (QA0 through QB1)
3.3 V or 2.5 V
V
DDCD
V
DDIC(1)
Supply voltage for output banks A and B (QC0 through QD1) and QFB
3.3 V or 2.5 V
1. V
DDIC
(Supply of FB_IN) must be equal to V
DDCD
(Supply of QFB) to ensure the SPO specification is met.
Supply voltage for differential inputs clock inputs CLK0 to CLK3 and FB_IN
3.3 V or 2.5 V
V
DDA
Clean supply for Analog portions of the PLL (This voltage is derived via an RC filter from the V
DD
supply) Derived from V
DD
Figure 5. MR Operation
MR
V
DD
t
reset_rel
t
reset_pulse
Figure 6. V
CC
Power Supply Bypass
V
DD
V
DDA
MPC9894
TBD
TBD
TBD
R
S
V
DD
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