- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376189 > MPC9894 (Electronic Theatre Controls, Inc.) Quad Input Redundant IDCS Clock Generator PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC9894 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Input Redundant IDCS Clock Generator |
| 中文描述： | 四路輸入冗余IDC機(jī)房，時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 20/28頁(yè) |
| 文件大小： | 367K |
| 代理商： | MPC9894 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)當(dāng)前第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)
Advanced Clock Drivers Devices
Freescale Semiconductor
20
MPC9894
Table 39. AC Characteristics (T
J
= –40°C to +110°C)
(1) (2)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
V
DD
= 3.3 V ±5%, V
DDAB,CD,IC
= 3.3 V ±5% or V
DDAB,CD,IC
= 2.5 V ±5%
Input and output timing specification
f
REF
Input reference frequency
Input reference frequency in PLL bypass mode
(3)
21.25
28.33
56.66
42.5
85.0
113.32
170
42.5
56.67
113.34
85
170
226.68
340
340
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Input_FB_Div[3:0] = 0
Input_FB_Div[3:0] = 1
Input_FB_Div[3:0] = 2
Input_FB_Div[3:0] = 3,4
Input_FB_Div[3:0] = 6,7,8
Input_FB_Div[3:0] = 10
Input_FB_Div[3:0] = 14,15
PLL bypass
f
VCO
VCO frequency range
(4)
340
680
MHz
f
MAX
Output Frequency
÷
2 output
÷
4 output
÷
8 output
÷
16 output
170.0
85.0
42.5
21.25
340.0
170.0
85.0
42.5
MHz
MHz
MHz
MHz
PLL locked
f
REFDC
Reference Input Duty Cycle
40
60
%
f
REFacc
Input Frequency Accuracy
(5)
5000
±
1600
ppm
mae
(
)
Misaligned Edge Specification
±
600
ps
t
r
, t
f
Output Rise/Fall Time
800
ps
20% to 80%
DC
Output duty cycle
47.5
50
52.5
%
f
I2C
I
2
C frequency range
400
kHz
Differential input and output voltages
V
PP
Differential input voltage
(6)
(peak-to-peak) (PECL)
1.3
V
V
PP, OK
Differential input voltage
(7)
(peak-to-peak) (PECL)
0.3
V
V
PP, NOK
Differential input voltage
(8)
(peak-to-peak) (PECL)
0.1
V
V
O(P-P)
Differential output voltage (peak-to-peak) (PECL)
0.3
0.8
V
PLL and IDCS specifications
t
(
)
Propagation Delay (static phase offset)
CLKX,
CLKX
to FB_IN,
FB_IN
–100
150
ps
PLL locked with external
feedback selected
t
sk(O)
Output-to-output Skew within a bank
(9)
Output-to-output Skew across a bank
(9)
50
100
ps
PER/CYC
Rate of change of period
(10)
÷
2 output
÷
4 output
÷
8 output
÷
16 output
+40
+80
+120
+160
±
40
±
80
±
120
±
160
ps
slew_control = 1
PER/CYC
Rate of change of period
(11)
÷
4 output
÷
8 output
÷
16 output
÷
2 output
ps
slew_control = 0
Jitter and bandwidth specifications
t
JIT(CC)
Cycle-to-cycle jitter
RMS (1
σ
)
10
ps
N = 2, 2, 2, 2
N = 4, 4, 4, 4
N = 8, 8, 8, 8
15
ps
N = 16, 16, 16, 16
t
JIT(PER)
Period Jitter
RMS (1
σ
)
10
ps
N = 2, 2, 2, 2
N = 4, 4, 4, 4
N = 8, 8, 8, 8
15
ps
N = 16, 16, 16, 16
t
JIT(
)
I/O Phase Jitter
RMS (1
σ
)
30
ps
BW
PLL closed loop bandwidth
(12)
2
MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPD400 | silicon diode |
| MPD200 | silicon diode |
| MPD201 | silicon diode |
| MPD202 | silicon diode |
| MPD203 | silicon diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9894VM | 制造商:IDT from Components Direct 功能描述:IDT MPC9894VM PLL - Trays 制造商:IDT 功能描述:IDT MPC9894VM PLL |
| MPC990 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC990F18 F44A WAF | 制造商:Motorola Inc 功能描述: |
| MPC991 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC991FA | 制造商:Motorola Inc 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。