
Advanced Clock Drivers Devices
Freescale Semiconductor
23
MPC9894
LOCK
PLL Lock Indicator
Output
LVCMOS
Low
V
DD
G10
CLK_STAT3
Input CLK3 status indicator
Output
LVCMOS
High
V
DD
H9
CLK_STAT2
Input CLK2 status indicator
Output
LVCMOS
High
V
DD
H10
CLK_STAT1
Input CLK1 status indicator
Output
LVCMOS
High
V
DD
G8
CLK_STAT0
Input CLK0 status indicator
Output
LVCMOS
High
V
DD
G9
SEL_STAT1
Reference Clock Selection Indicator (MSB)
Output
LVCMOS
High
V
DD
K8
SEL_STAT0
Reference Clock Selection Indicator (LSB)
Output
LVCMOS
High
V
DD
J8
BUSY
IDCS switch activity indicator
Activates I
2
C Boot Sequence
Output
LVCMOS
High
V
DD
J10
MBOOT
Input
LVCMOS
High
V
DD
D8
INT
Indicates any status IDCS change
Output
OD
n/a
V
DD
D9
PRESET
Sets preset state
Input
LVCMOS
High
V
DD
H7
TMS
JTAG Test Mode Select
Input
LVCMOS
High
V
DDIC
D3
TDI
JTAG Test Data Input
Input
LVCMOS
—
V
DDIC
H1
TRST
JTAG Test Reset Bar
Input
LVCMOS
Low
V
DD
H2
TCK
JTAG Test Clock
Input
LVCMOS
—
V
DDIC
G3
TDO
JTAG Test Data Out
Output
LVCMOS
—
V
DDIC
J3
SEL_2P5V
Indicate core VDD level,
(high = 2.5 V, low = 3.3 V)
Input
LVCMOS
—
V
DD
D7
MSTROUT_EN
Enable all outputs in sync
Input
LVCMOS
High
V
DD
K9
PLL_TEST2
PLL Test Bit 2
Input
LVCMOS
—
V
DDAB
H4
PLL_TEST1
PLL Test Bit 1
Input
LVCMOS
—
V
DDAB
G5
PLL_TEST0
PLL Test Bit 0 (LSB)
Input
LVCMOS
—
V
DDCD
D5
TPA
PLL Analog Test Pin
Output
Analog
—
V
DDA
E4
EX_FB_SEL
Select feedback mode (high = external)
Input
LVCMOS
—
V
DD
C7
V
DD
Control Input, Status Output and Core Supply
Power
—
—
V
DD
A10, B9, C3, C8,
G7, H8, J9, K10
V
DDA
Analog Supply
Power
—
—
V
DDA
E1
V
DDAB
Supply for A and B bank outputs
Power
—
—
V
DDAB
H6, J2, K2
V
DDCD
Supply for C and D bank outputs
Power
—
—
V
DDCD
A1, C4, C6
V
DDIC
Supply for input clocks
Power
—
—
V
DDIC
B2, H3, K1
GND
Control Input, Status Output and Core Ground
Ground
—
—
GND
A2, B1, B10, C5,
D4, D6, E5, E6,
F1, F4, F5, F6,
F7, G4, G6, H5,
J1, K3
Table 40. MPC9894 Pin Listing (Continued)
Signal Name
Description
Direction
Type
Active State
Supply
Pin