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參數(shù)資料
| 型號(hào)： | MPC9894 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Input Redundant IDCS Clock Generator |
| 中文描述： | 四路輸入冗余IDC機(jī)房，時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 25/28頁 |
| 文件大?。?/td> | 367K |
| 代理商： | MPC9894 |
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Advanced Clock Drivers Devices
Freescale Semiconductor
25
MPC9894
MPC9894 PROGRAMMING MODEL
Table 42. Slave Address (Register 0
—
Read Only)
Bit
7
6
5
4
3
2
1
0
Description
not used
ADDR_6
ADD_R5
ADDR_4
ADDR_3
ADDR_2
read from
ADDR[2] pin
ADDR_1
read from
ADR[1] pin
ADDR_0
read from
ADDR[0] pin
Reset default
x (TBD)
x (TBD)
x (TBD)
x (TBD)
Preset default
x (TBD)
x (TBD)
x (TBD)
x (TBD)
Table 43. Output Configuration Register (Register 1
—
Read/Write)
Bit
7
6
5
4
3
2
1
0
Description
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
FSEL_D[1:0]
Reset default
0
0
0
0
0
0
0
0
Preset default
0
0
0
0
1
0
1
0
Table 44. Mode Configuration and Alarm Reset Register (Register 2
—
Read/Write)
Bit
7
6
5
4
3
2
1
0
Description
not used
ALARM_RST[3:0] (See
Table 15
)
IDCS_MODE[2:0] (See
Table 16
)
Reset default
n/a
n/a
n/a
n/a
n/a
0
1
1
Preset default
n/a
n/a
n/a
n/a
n/a
1
0
0
Table 45. Device Configuration and Output Clock Enable Register (Register 3
—
Read/Write)
Bit
7
6
5
4
3
2
1
0
Description
INT_E
QUAL_EN
Slew_Control
Enable_QFB
ENABLE_QA
ENABLE_QB
ENABLE_QC
ENABLE_QD
Reset default
0
0
0
0
0
0
0
0
Preset default
1
1
0
0
1
1
1
1
Table 46I. nput and Feedback Divider Configuration Register (Register 4
—
Read/Write)
Bit
7
6
5
4
3
2
1
0
Description
Reserved
Reserved
Reserved
Reserved
Input_FB_Div[3:0]
Reset default
n/a
n/a
n/a
n/a
0
0
0
0
Preset default
n/a
n/a
n/a
n/a
0
0
1
1
Table 47. Status Register (Register 5
—
Read Only)
Bit
7
6
5
4
3
2
1
0
Description
INT
Inverse of
INT signal
CLK_STAT[3:0]
Status of CLK3, CLK2, CLK1 and CLK0 (sticky)
Copy of CLK_STAT[3:0] signal
LOCK
Inverse of LOCK
signal
SEL_STAT[1:0]
Copy of SEL_STAT[1:0]
signal
Table 48. Output Power-Up Register (Register 6 — Read/Write)
Bit
7
6
5
4
3
2
1
0
Description
PWR_QD1
PWR_QD0
PWR_QC1
PWR_QC0
PWR_QB1
PWR_QB01
PWR_QA1
PWR_QA0
Reset Default
0
0
0
0
0
0
0
0
Preset Default
1
1
1
1
1
1
1
1
Table 49. Feedback Power-Up Register (Register 7 — Read/Write)
Bit
7
6
5
4
3
2
1
0
Description
PWR_QFB
Reset Default
0
Preset Default
1
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