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參數(shù)資料
| 型號： | MPC9894 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Input Redundant IDCS Clock Generator |
| 中文描述： | 四路輸入冗余IDC機房，時鐘發(fā)生器 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 367K |
| 代理商： | MPC9894 |
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Advanced Clock Drivers Devices
Freescale Semiconductor
11
MPC9894
I
2
C INTERFACE AND CONFIGURATION/STATUS REGISTERS
The following tables summarize the bit configurations for
the registers accessible via the I
2
C interface. The register
values are read or written over the I
2
C interface by the I
2
C
Master. This sequence starts with the I
2
C start command,
followed by the I
2
C device address and read/write byte. This
is then followed by the address of the register that is to be
accessed. In the case of a write, the register address byte is
followed by the data to be written to that register. In the case
of a read, the device will then respond with the data from that
register. At the conclusion of the transfer an I
2
C Stop
command is issued by the Master to terminate the transfer.
For a complete description of the I
2
C protocol refer to the v2.1
I
2
C specification.
Table 10
lists the registers that are accessible via the I
2
C
interface.
Boot Mode
When the I
2
C boot mode is activated on power-up or reset
via the MBOOT pin, the entire set of writable configuration
registers are written with a 6-byte sequence. This sequence
starts with the Output Configuration Register, and is followed
by the Mode Configuration and Alarm Reset Register, the
Device Configuration and Output Clock Enable Register, the
Input and Feedback Divider Configuration Register, the
Output Power-Up Register and the Feedback Power-Up
Register. This equates to the register sequence of 1, 2, 3, 4,
6, 7. This sequence starts with the start command, the device
select and read/write(write) byte, followed by the beginning
byte address for reading from the EEPROM. This is then
followed by the start command, device select and read/write
(read) and four current address read bytes. The device
address is the binary 7-bit value of 1010000. This I
2
C
sequence is compatible with industry standard I
2
C bus
EEPROMs such as STMicroelectronics M24C01, or
equivalent.
Slave Address Register
The Slave Address register contains the I
2
C address that
is used to determine if the data on the I
2
C interface is
addressed to this device. The seven-bit address is
determined with the fixed value of binary 1101 followed by
variable bits that are obtained from the three address pins.
The three input pins allow for 8 different addresses for a given
clock generator, allowing up to 8 clock generators to be
addressed on a single I
2
C interface.
Table 10. I
2
C Registers
Address
Register
0x00
Table 11. Slave Address (Register 0 — Read Only)
0x01
Table 12. Output Configuration Register (Register 1 — Read/Write)
0x02
Table 14. Mode Configuration and Alarm Reset Register (Register 2 — Read/Write)
0x03
Table 17. Device Configuration and Output Clock Enable Register (Register 3 — Read/Write)
0x04
Table 22. Input and Feedback Divider Configuration Register (Register 4 — Read/Write)
0x05
Table 24. Status Register (Register 5 — Read Only)
0x06
Table 25. Output Power-Up Register (Register 6 — Read/Write)
0x07
Table 27. Feedback Power-Up Register (Register 7 — Read/Write)
Start
Write
Start
Read
Stop
ACK
ACK
ACK
NoACK
Dev Selection
Dev Selection
Data Out
Byte Addr
Figure 4. Boot Mode Random Access Read
Table 11. Slave Address (Register 0
—
Read Only)
Bit
7
6
5
4
3
2
1
0
Description
not used
ADDR_6
ADD_R5
ADDR_4
ADDR_3
ADDR_2
read from
ADDR[2] pin
ADDR_1
read from
ADR[1] pin
ADDR_0
read from
ADDR[0] pin
Reset default
1
1
0
1
Preset default
1
1
0
1
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