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參數(shù)資料
| 型號： | MPC9894 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Input Redundant IDCS Clock Generator |
| 中文描述： | 四路輸入冗余IDC機房，時鐘發(fā)生器 |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 367K |
| 代理商： | MPC9894 |
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Advanced Clock Drivers Devices
Freescale Semiconductor
3
MPC9894
Control Inputs and Outputs
EX_FB_SEL
Input
LVCMOS
Selects between external feedback and internal feedback
V
DD
high
CLK_VALID[3:0]
(1)
Input
LVCMOS
Validates the clock inputs CLK0 to CLK3 (internal pullup)
V
DD
high
CLK_ALARM_RST
Input
LVCMOS
Reset of all four alarm status flags and clock selection status flag
(internal pullup)
V
DD
low
PLL_BYPASS
Input
LVCMOS
Select static test mode (internal pulldown)
V
DD
high
MEDIA
Input
LVCMOS
Output impedance control
V
DD
high
MR
Input
LVCMOS
Device reset (internal pullup)
V
DD
low
LOCK
Output
LVCMOS
PLL lock indicator
V
DD
low
CLK_STAT[3:0]
Output
LVCMOS
Clock input status indicator
V
DD
high
SEL_STAT[1:0]
Output
LVCMOS
Reference clock selection indicator
V
DD
high
BUSY
Output
LVCMOS
IDCS switching activity indicator
V
DD
low
MBOOT
Input
LVCMOS
Activates I
2
C boot sequence (internal pulldown)
V
DD
high
PRESET
Input
LVCMOS
Enables Preset configuration of configuration registers on release of
MR
(internal pulldown)
V
DD
high
INT
Output
OD
Indicate any status IDCS change
V
DD
low
MSTROUT_EN
Input
LVCMOS
Master Enable for all Outputs (internal pulldown)
V
DD
high
SEL_2P5V
Input
LVCMOS
Device core power supply selection for VDD and VDDA
V
DD
high
I
2
C Interface
SCL
I/O
OD
I
2
C interface control, clock
V
DD
—
SDA
I/O
OD
I
2
C interface control, data
V
DD
—
ADDR[2:0]
Input
LVCMOS
I
2
C interface address lines (10K pullup)
V
DD
high
IEEE 1149.1 and Test
TMS
Input
LVCMOS
JTAG test mode select (10K pullup)
V
DDIC
—
TDI
Input
LVCMOS
JTAG test data input (10K pullup)
V
DDIC
—
TDO
Output
LVCMOS
JTAG test data output
V
DDIC
—
TCK
Input
LVCMOS
JTAG test clock
V
DDIC
—
TRST
Input
LVCMOS
JTAG test reset (10K pullup)
V
DDIC
—
PLL_TEST[2:0]
Input
LVCMOS
PLL_TEST pins (factory use only, MUST BE CONNECTED TO GND)
N/A
—
TPA
Output
LVCMOS
PLL Analog test pin (factory use only, LEAVE OPEN)
V
DDA
—
Power and Ground
GND
Supply
Ground
Negative power supply
—
—
V
DD
Supply
—
Positive power supply for the device core, output status and control
inputs. (3.3 V or 2.5 V)
—
—
V
DDAB
Supply
—
Supply voltage for output banks A and B (QA0 through QB1)
(3.3 V or 2.5 V)
—
—
V
DDCD
Supply
—
Supply voltage for output banks C and D (QC0 through QD1) and QFB
(3.3 V or 2.5 V)
—
—
V
DDIC
Supply
—
Supply voltage for differential inputs clock inputs CLK0 to CLK3 and
FB_IN (3.3 V or 2.5 V)
—
—-
V
DDA
Supply
—
Clean supply for analog portions of the PLL (This voltage is derived via
a RC filter from the V
DD
supply)
—
—
1. bit order = msb to lsb.
Table 1. Pin Configurations (Continued)
Pin
I/O
Type
Function
Supply
Active State
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