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參數(shù)資料
| 型號(hào)： | MPC9894 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Input Redundant IDCS Clock Generator |
| 中文描述： | 四路輸入冗余IDC機(jī)房，時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 367K |
| 代理商： | MPC9894 |
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Advanced Clock Drivers Devices
Freescale Semiconductor
10
MPC9894
INPUT AND OUTPUT FREQUENCY CONFIGURATION
Configuring the MPC9894 input and output frequencies
requires programming the internal PLL input, feedback and
output dividers. The output frequency is represented by the
following formula:
f
OUT
= [(f
REF
÷
P)
M]
÷
N
where f
REF
is the reference frequency of the selected input
clock source (reference input), M is the PLL feedback divider
and N is an output divider. The PLL input divider P, the
feedback divider M and the output divider are configured by
the device registers 1 and 4. The MPC9894 has four output
banks (Bank A, B, C, and D) and each output bank can be
configured individually as shown in
Table 8
.
The reference frequency f
REF
and the selection of the PLL
input divider (P) and feedback-divider (M) is limited by the
specified VCO frequency range. f
REF
, P and M must be
configured to match the VCO frequency range of 340 to
680 MHz in order to achieve stable PLL operation:
f
VCO,MIN
≤
(f
REF
÷
P
M)
≤
f
VCO,MAX
The PLL input divider (P) can be used to situate the VCO
in the specified frequency range. The PLL input divider
effectively extends the usable input frequency range.
The output frequency for each bank can be derived from
the VCO frequency and output divider (N):
f
QA
[1:0] = f
VCO
÷
N
A
f
QB
[1:0] = f
VCO
÷
N
B
f
QC
[1:0] = f
VCO
÷
N
C
f
QD
[1:0] = f
VCO
÷
N
D
Table 9
illustrates the possible input clock frequency
configurations of the MPC9894. Note that the VCO lock
range is always 340 MHz to 680 MHz, setting lower and
upper boundaries for the frequency range of the device.
Figure 3. PLL Frequency Calculation
÷
M
÷
N
f
REF
f
OUT
÷
P
PLL
Table 8. Configuration of PLL P, M and N Frequency Dividers
Divider
Available Values
Configuration Through
PLL Input Divider (P)
÷
1,
÷
2,
÷
3,
÷
4,
÷
6
Input_FB_Div[3:0], Register 4, bit 3:0
PLL Feedback Divider (M)
÷
8,
÷
12,
÷
16
PLL Output Divider, Bank A (N
A
)
PLL Output Divider, Bank B (N
B
)
PLL Output Divider, Bank C (N
C
)
PLL Output Divider, Bank D (N
D
)
÷
2,
÷
4,
÷
8,
÷
16
FSEL_B[1:0], Register 1, bit 7:6
÷
2,
÷
4,
÷
8,
÷
16
FSEL_B[1:0], Register 1, bit 5:4
÷
2,
÷
4,
÷
8,
÷
16
FSEL_C[1:0], Register 1, bit 3:2
÷
2,
÷
4,
÷
8,
÷
16
FSEL_D[1:0], Register 1, bit 1:0
Table 9. Input and Output Frequency Ranges
Input_FB_Div[3:0]
P
M
f
REF
range
MHz
Output frequency for any bank A, B, C or D (FSEL_x) and ratio to f
REF
N = 2
N = 4
N = 8
N = 16
0
÷
1
÷
16
21.25 – 42.5
8
f
REF
6
f
REF
3
f
REF
4
f
REF
4
f
REF
4
f
REF
3
f
REF
1.5
f
REF
2
f
REF
2
f
REF
2
f
REF
1.5
f
REF
0.75
f
REF
1
f
REF
1
f
REF
f
REF
1
÷
1
÷
12
28.33 – 56.67
0.75
f
REF
0.375
f
REF
0.5
f
REF
0.5
f
REF
2
÷
2
÷
12
56.66 – 113.34
3
÷
1
÷
8
42.5 – 85.0
4
÷
2
÷
16
42.5 – 85.0
5
reserved
6
÷
2
÷
8
85.0 – 170.0
2
f
REF
2
f
REF
2
f
REF
1
f
REF
1
f
REF
1
f
REF
0.5
f
REF
0.5
f
REF
0.5
f
REF
0.125
f
REF
0.125
f
REF
0.125
f
REF
7
÷
3
÷
12
85.0 – 170.0
8
÷
4
÷
16
85.0 – 170.0
9
reserved
10
÷
4
÷
12
113.32 – 226.64
1.5
f
REF
0.75
f
REF
0.375
f
REF
0.1875
f
REF
11
reserved
12
reserved
13
reserved
14
4
÷
8
170.0 – 340.0
1
f
REF
1
f
REF
0.5
f
REF
0.5
f
REF
0.25
f
REF
0.25
f
REF
0.125
f
REF
0.125
f
REF
15
6
÷
12
170.0 – 340.0
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