- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376189 > MPC9894 (Electronic Theatre Controls, Inc.) Quad Input Redundant IDCS Clock Generator PDF資料下載
參數(shù)資料
| 型號： | MPC9894 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Input Redundant IDCS Clock Generator |
| 中文描述： | 四路輸入冗余IDC機(jī)房，時鐘發(fā)生器 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 367K |
| 代理商： | MPC9894 |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
Advanced Clock Drivers Devices
Freescale Semiconductor
4
MPC9894
Table 2. Function Table
Control
Default
0
1
Control Inputs
PLL_BYPASS
0
PLL enabled. The input to output frequency
relationship is according to
Table 9
if the PLL is
frequency locked.
PLL bypassed and IDCS disabled. The VCO output is
replaced by the reference clock signal f
REF
. This is
considered to be a test mode and clock monitoring and
clock switching are disabled during this operation.
CLK_VALID[3:0]
0
The associated clock input is considered to be invalid
and usable
The associated clock input is considered to be a valid
usable clock input
CLK_ALARM_RST
1
CLK_STAT[3:0] and SEL_STAT[1:0] flags are reset:
CLK_STAT[3:0] = 0000 and SEL_STAT[1:0] = 00.
CLK_ALARM_RST is a one-shot function.
CLK_STAT[3:0] and SEL_STAT[1:0] flags are active
MR
1
Reset of data generators and output dividers. The
MPC9894 requires reset at power-up and after any
loss of PLL lock. Loss of PLL lock may occur when the
external feedback path is interrupted. The length of the
reset pulse should be greater than two reference clock
cycles
I
2
C read/write mode
Outputs enabled (active)
MBOOT
0
I
2
C boot mode
PRESET
0
Normal Operation
Uses Configuration Register PRESET values on MR
EX_FB_SEL
0
Selects internal feedback path
Selects external feedback path
MEDIA
0
Low output impedance (QA0 to QD1 and QFB)
50
output impedance (QA0 to QD1 and QFB)
SEL_2P5V
0
Selects 3.3 V for core V
DD
Selects 2.5 V for core V
DD
MSTROUT_EN
All outputs disabled (synchronous with clock being low) All outputs enabled
Control Outputs
LOCK
(1)
1. The combined pins of LOCK = 1 and BUSY = 0 are used to indicate a catastrophic failure. Refer to
PLL Out-of-Lock Conditions
.
PLL is locked
PLL is unlocked
BUSY
(1)
The IDCS has initiated a clock switch.
No clock switch currently performed
INT
IDCS status has changed (indicates an assertion of
CLK_STAT[3:0] or deassertion of
LOCK
)
No status change
CLK_STAT[3:0]
Associated clock input not valid
Associated clock input valid
SEL_STAT[1:0]
Encoded value refer to
Table 7
Encoded value refer to
Table 7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPD400 | silicon diode |
| MPD200 | silicon diode |
| MPD201 | silicon diode |
| MPD202 | silicon diode |
| MPD203 | silicon diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9894VM | 制造商:IDT from Components Direct 功能描述:IDT MPC9894VM PLL - Trays 制造商:IDT 功能描述:IDT MPC9894VM PLL |
| MPC990 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC990F18 F44A WAF | 制造商:Motorola Inc 功能描述: |
| MPC991 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC991FA | 制造商:Motorola Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。