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參數(shù)資料
| 型號： | MPC9894 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Input Redundant IDCS Clock Generator |
| 中文描述： | 四路輸入冗余IDC機(jī)房，時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大小： | 367K |
| 代理商： | MPC9894 |
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Advanced Clock Drivers Devices
Freescale Semiconductor
12
MPC9894
Output Configuration Register
The output configuration register is divided into four,
2 bit-groups with each group selecting the divide ratio for
output banks A through bank D, refer to
Table 12
. For each
bank, four output divider settings (
÷
2,
÷
4,
÷
8,
÷
16) are
available, refer to
Table 12
.
Mode Configuration Register
The mode configuration register, refer to
Table 14
, is a
read/write register and contains the fields for mode selection
as well as alarm reset.
The mode of the MPC9894 may be changed by writing the
three least significant Mode Configuration Register bits to the
desired value. The current idcs mode of the MPC9894 may
be obtained by reading this register.
The alarm reset bits, found in bit positions 6 thru 3, may be
used to individually reset the status flags of register 5. Each
of these flag bits are associated with the four clock inputs pins
and indicate a failed clock input. Clearing of a clock status
flag is performed by writing a logic 1 to the individual bit (or
bits if more than one flag is to be cleared). Care should be
taken to insure that the idcs mode information is written to the
proper value when resetting the clock status bits. The four
alarm reset bits always read as a logic 0. If a clock input
status flag is cleared and the clock input is still in a failed
state, the status flag will go set within 4 clock cycles after
being cleared.
Table 12. Output Configuration Register (Register 1
—
Read/Write)
Bit
7
6
5
4
3
2
1
0
Description
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
FSEL_D[1:0]
Reset default
0
0
0
0
0
0
0
0
Preset default
0
0
0
0
1
0
1
0
Table 13. PLL Output Divider N (FSEL_A to FSEL_D)
FSEL_x[1:0]
Value
00
÷
2
01
÷
4
10
÷
8
11
÷
16
Table 14. Mode Configuration and Alarm Reset Register (Register 2
—
Read/Write)
Bit
7
6
5
4
3
2
1
0
Description
not used
ALARM_RST[3:0] (Refer to
Table 15
)
IDCS_MODE[2:0] (Refer to
Table 16
)
Reset default
n/a
n/a
n/a
n/a
n/a
0
1
1
Preset default
n/a
n/a
n/a
n/a
n/a
1
0
0
Table 15. Individual Reset of CLK_STAT[x] Bits
ALARM_RST[x]
Description
0
No action
1
The status flag CLK_STAT[x] is cleared by setting of this bit. (bit always reads as zero)
Table 16. MPC9894 IDCS Configuration
(1)
1. This is a repeat of
Table 8
.
2. For CLK_VALID[3:0] = 1111 and input clock validity.
IDCS_MODE [2:0]
Description
Primary clock
Secondary clock
(2)
Tertiary clock
(2)
Quaternary clock
(2)
000
Manual
CLK0
n/a
n/a
n/a
001
CLK1
n/a
n/a
n/a
010
CLK2
n/a
n/a
n/a
011
CLK3
n/a
n/a
n/a
100
Automatic
CLK0
CLK1
CLK2
CLK3
101
CLK1
CLK2
CLK3
CLK0
110
CLK2
CLK3
CLK0
CLK1
111
CLK3
CLK0
CLK1
CLK2
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