
Advanced Clock Drivers Devices
Freescale Semiconductor
19
MPC9894
Table 37. PECL DC Characteristics (T
J
= –40°C to +110°C)
(1)
1. DC characteristics are design targets and pending characterization.
2. Clock inputs driven by PECL compatible signals.
3. V
PKPK
is the minimum differential input voltage swing required to maintain AC characteristics.
4. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential PECL clock inputs (CLKx,
CLKx
and FB_IN,
FB_IN
)
(2)
for V
DDIC
= 3.3 V ±5% or V
DDIC
= 2.5 V ±5%
AC Differential Input Voltage
(3)
V
PKPK
0.2
1.3
V
Differential operation
V
CMR
Differential Cross Point Voltage
(4)
1.25
V
DD
–0.3
V
Differential operation
I
IN
Input Current
(1)
±100
μ
A
V
PP
= 0.8 V and
V
CMR
= V
DDL
–0.7 V
Differential PECL clock outputs (QA0 to QD1 and QFB) for V
DDAB,CD
= 3.3 V ±5% or V
DDAB,CD
= 2.5 V ±5%
V
OH
Output High Voltage
V
DDAB,CD
–1.2
V
DDAB,CD
–0.7
V
Termination 50
to V
TT
V
OL
Output Low Voltage
3.3
2.5
V
DDAB,CD
–2.0
–1.9
V
DDAB,CD
–1.5
–1.4
V
Termination 50
to V
TT
Z
OUT
Output Impedance
Z
diff
MEDIA = 0
MEDIA = 1
50
80
See
Figure 7
See
Figure 8
Table 38. LVCMOS I/O DC Characteristics (T
J
= –40°C to +110°C)
(1)
1. DC characteristics are design targets and pending characterization.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Single-ended LVCMOS inputs for V
DD
= 3.3 V ±5%
V
IH
Input High Voltage
2.0
V
DD
+ 0.3
V
LVCMOS
V
IL
Input Low Voltage
0.8
V
LVCMOS
V
OH
Output High Voltage
2.4
V
I
OH
= –6 mA
V
OL
Output Low Voltage
0.4
V
I
OL
= 6 mA
Single-ended LVCMOS inputs for V
DD
= 2.5 V ±5%
V
IH
Input High Voltage
1.7
V
DD
+ 0.3
V
LVCMOS
V
IL
Input Low Voltage
0.7
V
LVCMOS
V
OH
Output High Voltage
1.9
V
I
OH
= –6 mA
V
OL
Output Low Voltage
0.4
V
I
OL
= 6 mA