參數(shù)資料
型號(hào)： MPC9894
廠商： Electronic Theatre Controls, Inc.
英文描述： Quad Input Redundant IDCS Clock Generator
中文描述： 四路輸入冗余IDC機(jī)房，時(shí)鐘發(fā)生器
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 367K
代理商： MPC9894
Advanced Clock Drivers Devices
Freescale Semiconductor
13
MPC9894
Device Configuration and Output Enable Register
The Device Configuration and Output Enable Register is
used to individually enable or disable each bank of outputs.
Output banks are enabled by setting the corresponding bit to
a logic 1 and disabled by setting the bit to a logic 0 as
described in
Table 21. Output Clock Stop/Enable
. The
disable logic sets the outputs of the addressed bank
synchronously to logic low state (Qx[] = 0 and Qx[] = 1). The
clock output enable/stop bits can be set asynchronous to any
clock signal without the risk of generating of runt pulses. The
PLL feedback output QFB cannot be disabled when
MPC9894 is configured for external feedback.
The Device Configuration Register, bit 6, QUAL_EN is
used to enable or disable all clock input qualifier pins.
Asserting this bit enables the Clock Qualifier Input Pins
CLK_VALID[3:0]. Deasserting this bit disables these pins
such that inputs on CLK_VALID[3:0] are ignored.
The INT_E bit, in bit position 7, is used to enable or disable
interrupts from occurring on the INT pin. The setting of the
interrupt flag (bit 7 of the Status Register) is unaffected by this
bit.
Table 17. Device Configuration and Output Clock Enable Register (Register 3
—
Read/Write)
Bit
7
6
5
4
3
2
1
0
Description
INT_E
QUAL_EN
Slew_Control
Enable_QFB
ENABLE_QA
ENABLE_QB
ENABLE_QC
ENABLE_QD
Reset default
0
0
0
0
0
0
0
0
Preset default
1
1
0
0
1
1
1
1
Table 18. Interrupt Signal (INT) Enable INT_E
INT_E
Description
0
Interrupt signal
INT
is disabled
1
Interrupt signal
INT
is enabled
Table 19. Input Clock Qualifier Enable QUAL_EN
QUAL_EN
Description
0
CLK_VALID[3:0] are disabled (clock qualifier signals are disabled)
1
CLK_VALID[3:0] are enabled (clocks can be qualified)
Table 20. Slew Control
Slew_Control
Description
0
Clock slew direction on clock switch is toward the closest edge
1
Clock slew direction on clock switch is toward the lagging edge
Table 21. Output Clock Stop/Enable
ENABLE_Qx
Description
0
Output bank x is disabled (clock stop in logic low state)
1
Output bank x is enabled
相關(guān)PDF資料
PDF描述
MPD400 silicon diode
MPD200 silicon diode
MPD201 silicon diode
MPD202 silicon diode
MPD203 silicon diode
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC9894VM 制造商:IDT from Components Direct 功能描述:IDT MPC9894VM PLL - Trays 制造商:IDT 功能描述:IDT MPC9894VM PLL
MPC990 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER
MPC990F18 F44A WAF 制造商:Motorola Inc 功能描述:
MPC991 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER
MPC991FA 制造商:Motorola Inc 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*