
Communication Processor Module
16-10
MPC823 USER’S MANUAL
MOTOROLA
RISC
COMMUNICATION
16
PROCESSOR
MODULE
16.2.7 RISC Microcontroller Commands
To initialize the serial channel or DMA, you can issue a command to the CPM command
register. The command you issue will ask the communication processor module to perform
further device-specific functions based on the information in the device’s parameter RAM.
16.2.7.1 CPM COMMAND REGISTER. The core sets the FLG bit in the 16-bit,
memory-mapped, read/write CPM command register (CPCR) when it issues a command
and the communication processor module clears the FLG bit when the command is
completed. The core is now ready for the next command. Subsequent commands to the
CPCR can only be given when the FLG bit is clear. When issuing the software reset
command, the core should also set the FLG bit.
RST—Software Reset Command
This bit is set by the core and cleared by the communication processor module and when
this command is executed, the RST and FLG bits are cleared within two general system
clocks. The RISC reset routine is approximately 60 clocks long, but you can start initializing
the communication processor module immediately after this command is issued. RST is
useful when the core wants to reset the registers and parameters for all the channels as well
as the RISC microprocessor and timer tables. However, this bit does not affect the serial
interface or parallel I/O registers.
0 = No reset is issued.
1 = Reset is issued.
Bits 1–3—Reserved
These bits are reserved and should be set to 0.
OPCODE—Operation Code
This field is used in conjunction with the CH_NUM field to define a command sent to the
CPM. It issues a variety of commands, which are described in
Table 16-2. For the same
operation code, the results may be different, depending on the channel number you select.
For example, if your operation code is 0101 (GRACEFUL STOP TX) and your channel
number is set to 0100 (SCC2), then the operation will gracefully stop the transmit on SCC2.
If your channel number is set to 0001 (IDMA1), then the operation will gracefully stop the
transmit on IDMA1.
CPCR
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIELD
RST
RESERVED
OPCODE
CH_NUM
RESERVED
FLG
RESET
00
0
00
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0x9C0