
Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-189
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
The DPLL has a carrier-sense signal that indicates when there are data transfers on the
RXD2 signal. Using the TSNC field of the GSMR_L, this signal is asserted as soon as a
transition is detected on RXD2 and it is negated after a programmable number of clocks
have been detected with no transitions.
To prevent itself from locking on the wrong edges and to provide fast synchronization, the
DPLL should receive a preamble pattern before it receives the data. In some protocols, the
preceding flags or syncs are used. However, some protocols require a special pattern, such
as alternating ones and zeros. When a transmission occurs, the serial communication
controller can generate preamble patterns as programmed in the TPP and TPL bits of the
GSMR_L.
In addition, the DPLL can be used to invert the datastream of a reception or transmission.
This feature is available in all encodings, including the standard NRZ data format. Also,
when the transmitter is idle, the DPLL can either force the TXD2 signal to a high voltage or
continue encoding the data supplied to it. The DPLL is used for UART encoding/decoding,
which gives you the option of selecting the divide ratio in the UART decoding process (8
×,
16
×, or 32×). Typically, 16× option is used.
The maximum data rate that can be supported with the DPLL is 3.125MHz when operating
with a 25MHz system clock, assuming that the 8
× option is chosen
(25MHz
÷ 8 = 3.125MHz). Thus, the frequency applied to the CLKx pin or generated by an
internal baud rate generator may be up to 25MHz on a 25MHz MPC823, if the DPLL 8
×, 16×,
or 32
× options are used.
Table 16-25. Preamble Patterns for Decoding Methods
DECODING METHOD
PREAMBLE PATTERN
MAXIMUM PREAMBLE
LENGTH REQUIRED
NRZI Mark
All zeros
8-bit
NRZI Space
All ones
8-bit
FM0
All ones
8-bit
FM1
All zeros
8-bit
Manchester
Repeating 10’s
8-bit
Differential Manchester
All ones
8-bit
Note: The 1:2 ratio of GCLK1 to the serial clock does not apply when the DPLL is used
to recover the clock in the 8
×, 16×, or 32× modes. Synchronization occurs
internally after the receive clock is generated by the DPLL. Therefore, even the
fastest DPLL clock generation (the 8
× option) easily meets the required 1:2 ratio
clocking limit.