
Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-187
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
16.9.10.2 ASYNCHRONOUS PROTOCOLS. In asynchronous protocols, the RTS pin is
asserted when SCC2 data is loaded into the transmit FIFO and a falling transmit clock
occurs. The CD and CTS pins can be used to control reception and transmission in the same
manner as the synchronous protocols. The first bit of data transmission in an asynchronous
protocol is the start bit of the first character. In addition, the UART protocol has an option for
If CTS is already asserted when RTS is asserted, transmission begins in two additional
bit times. However, if CTS is not already asserted when RTS is asserted and CTSS = 0, then
transmission begins in three additional bit times. If CTS is not already asserted when RTS
is asserted and CTSS = 1 in the GSMR_H, then transmission begins in two additional bit
times.
16.9.11 Digital Phase-Locked Loop Operation
Each SCC2 channel includes a digital phase-locked loop (DPLL) that is used to recover
clock information from a received datastream. For applications that provide a direct clock
source to the serial communication controller, the DPLL can be bypassed if it is programmed
to do so in the GSMR_L. The DPLL must not be used when the serial communication
controller is programmed to Ethernet and it is optional for other protocols. The DPLL receiver
block diagram is illustrated in
Figure 16-68 and the transmitter block diagram is in
The DPLL can be driven by an external clock or one of the baud rate generator outputs and
they should be approximately 8
×, 16×, or 32× the data rate, depending on the encoding or
decoding preferred. The DPLL uses this clock, along with the datastream, to construct a
data clock that can be used as the SCC2 receive and/or transmit clock. In all modes, the
DPLL uses the input clock to determine the nominal bit time.
At the beginning of operation, the DPLL is in search mode, whereas the first transition resets
the internal DPLL counter and begins DPLL operation. While the counter is counting, the
DPLL watches the incoming datastream for transitions and when a transition is detected, the
DPLL makes a count adjustment to produce an output clock that tracks the incoming bits.