
Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-183
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
3. Extract data from the RX buffer descriptor if the RX, RXB, or RXF bit is set in the SCCE
register. If the receive speed is fast or the interrupt delay is long, more than one
receive buffer may have been received by the serial communication controller. Thus,
it is important to check more than just one RX buffer descriptor during interrupt
handling. One common practice is to process all RX buffer descriptors in the interrupt
handler until one is found with its E bit set.
4. Reset the status bit in the buffer descriptor’s control and status field that is associated
with the interrupt. These bits do not set reset after each I/O operation.
5. Clear the SCC2 bit in the CISR.
6. Execute the rfi instruction.
16.9.10 Controlling SCC2 Timing
When the DIAG field of the GSMR_L are programmed to normal operation, the CD and CTS
signals are automatically controlled by the serial communication controller. It is assumed
that the TCI bit of the GSMR_L is cleared, which implies a normal transmit clock operation.
16.9.10.1 SYNCHRONOUS PROTOCOLS. In synchronous protocols, the RTS pin is
asserted when the serial communication controller data is loaded into the transmit FIFO and
a falling transmit clock occurs. At this point, the serial communication controller starts
transmitting data once the appropriate conditions occur on the CTS pin. In all cases, the first
bit of data is the start of the opening flag, sync pattern, or preamble.
Figure 16-64 illustrates that the delay between the RTS pin and data is 0 bit times,
regardless of how the CTSS bit is set in the GSMR_H. This operation assumes that the CTS
pin is already asserted to the serial communication controller or that the CTS pin is
reprogrammed to be a parallel I/O line, in which case the CTS signal to the serial
communication controller is always asserted. The RTS pin is negated one clock after the last
bit in the frame.
Figure 16-64. RTS Output Delays Asserted for Synchronous Protocols
TXD2
RTS
CTS
FIRST BIT OF FRAME DATA
(INPUT)
TCLK
(OUTPUT)
NOTE: A frame includes opening and closing flags and syncs, if present in the protocol.
LAST BIT OF FRAME DATA