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Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-327
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
16.9.22.12 INTERPACKET GAP TIME. The minimum interpacket gap time for
back-to-back transmission is 9.6
s. The receiver receives back-to-back frames with this
minimum spacing. In addition, after the backoff algorithm, the transmitter waits for carrier
sense to be negated before retransmitting the frame. Retransmission begins 9.6
s after
carrier sense is negated if it stays negated for at least 6.4
s.
16.9.22.13 HANDLING COLLISIONS. If a collision occurs while a frame is being
transmitted, the SCC2 Ethernet controller continues transmitting for at least 32 bit times,
thus transmitting a JAM pattern that consists of 32 ones. If the collision occurs during the
preamble sequence, the JAM pattern will be sent at the end of the preamble sequence.
If a collision occurs within 64 byte times, the retry process is initiated. The transmitter waits
a random number of slot times (512 bit times or 52
s). If a collision occurs after 64 byte
times, then no retransmission is performed and the buffer is closed with an LC error
indication. If a collision occurs while a frame is being received, reception stops. This error is
only reported in the buffer descriptor if the length of this frame is greater than or equal to the
MINFLR or if the RSH mode is enabled in the PSMR–SCC2 Ethernet.
16.9.22.14 LOOPBACK AND FULL-DUPLEX OPERATION. Both internal and external
loopback is supported by the SCC2 Ethernet controller. In loopback mode, both of the SCC2
FIFOs are used and the channel actually operates in a full-duplex fashion. Both internal and
external loopback are configured using combinations of the LPB bit in the PSMR–SCC2
Ethernet and the DIAG field in the GSMR_L.
Internal loopback disconnects the serial communication controller from the serial interface.
The receive data is connected to the transmit data and the receive clock is connected to the
transmit clock. Both FIFOs are used. The transmitted data from the transmit FIFO is
received immediately into the receive FIFO. There is no heartbeat check in this mode. TENA
should be configured as a general-purpose output, and the HBC bit in the PSMR–SCC2
Ethernet should be zero.
In external loopback operation, the SCC2 Ethernet controller listens for data being received
from the EEST at the same time that it is transmitting.