
Communication Processor Module
16-322
MPC823 USER’S MANUAL
MOTOROLA
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
RFBD_PTR—For internal use only. This register contains the first RX buffer descriptor
pointer.
TFBD_PTR—For internal use only. This register contains the first TX buffer descriptor
pointer.
TLBD_PTR—For internal use only. This register contains the last TX buffer descriptor
pointer.
TX_LEN—For internal use only.
IADDR1–4 —These four registers are used in the hash table function of the individual
addressing mode. You can write zeros to these values after reset and before the
Ethernet channel is enabled to disable all individual hash address recognition functions.
The SET GROUP ADDRESS command is used to enable the hash table.
BOFF_CNT—For internal use only.
TADDR—This parameter allows you to add and delete addresses from the individual
and group hash tables. After placing an address in TADDR, you must issue the SET
GROUP ADDRESS command. TADDR_L is the lowest order half-word and TADDR_H
is the highest order half-word.TADDR_M is the middle half-word.
16.9.22.8 CONFIGURING THE SCC2 ETHERNET PARAMETERS. You configure the
SCC2 to operate as an SCC2 Ethernet controller by setting the MODE field in the general
SCC2 mode low register (GSMR_L). The receive errors are reported in the RX buffer
descriptor and the transmit errors are reported in the TX buffer descriptor. Several fields in
the GSMR_H and GSMR_L must be programmed to special values for Ethernet. You should
program the data synchronization register (DSR) using the table below. The GSMR_L
programs the first six bytes of the preamble and the SYN1 field of the DSR programs the
seventh byte (ox55) of the preamble. Program the 1-byte start delimiter with the value 0xD5
for more information.
SYN2—Synchronization 2
This field represents the start frame delimiter for an Ethernet frame. You must set this field
to 0xD5.
SYN1—Synchronization 1
This field represents the seventh byte of the preamble for the Ethernet frame. You must set
this field to 0x55.
DSR
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIELD
SYN2
SYN1
RESET
0111111001111110
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0xA2E