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Communication Processor Module
16-272
MPC823 USER’S MANUAL
MOTOROLA
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
CRC Error—When this error occurs, the channel writes the received cyclic redundancy
check to the data buffer, closes the buffer, and sets the CR bit in the buffer descriptor
and the RXF bit in the SCCE–ASYNC HDLC register. After receiving a signal unit with
this error, the receiver gets ready to receive the next frame.
Break Sequence Received Error—This error occurs when the UART receiver finds the
first character of a break sequence. The channel closes the buffer by setting the RX
BRK bit in the buffer descriptor and the RXF bit in the SCCE–ASYNC HDLC register.
The CRC error status condition is not checked. The BRKSbit is set in the
SCCE–ASYNC HDLC register when the first break of a sequence is found and the
BRKE is set when an idle bit is received after a break sequence.
16.9.19.12 PROGRAMMING THE SCC2 ASYNC HDLC CONTROLLER.
16.9.19.12.1 SCC2 ASYNC HDLC Mode Register. When the SCC2 is in asynchronous
HDLC mode, the 16-bit, memory-mapped, read/write protocol-specific mode register is
referred to as the SCC2 ASYNC HDLC mode (PSMR–SCC2 ASYNC HDLC) register. It
controls asynchronous HDLC mode-specific parameters. Since each protocol has specific
requirements, the PSMR bits are different for each implementation.
FLC—Flow Control
0 = Normal operation.
1 = Asynchronous flow control. When the CTS pin is negated, the transmitter stops at
the end of the current character. If CTS is negated past the middle of the current
character, the next full character can be sent and transmission stops. When CTS
is asserted once more, transmission continues where it left off and no CTS lost
error is reported. No characters, except idles, are transmitted while CTS is
negated.
Bits 1 and 4–15—Reserved
These bits are reserved and should be set to 0.
CHLN—Character Length
For asynchronous HDLC and IrLAP modes, these bits must be set to 1.
PSMR–SCC2 ASYNC HDLC
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIELD
FLC
RES
CHLN
RESERVED
RESET
00
0
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0xA28