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Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-171
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
16.9.4 Data Synchronization Register
The serial communication controller has a 16-bit, memory-mapped, read/write data
synchronization register (DSR) that specifies the pattern used in the frame synchronization
procedure of the synchronous protocols. In the UART protocol, it is used to configure
fractional stop bit transmission. In the Transparent protocol, it should be programmed with
the preferred Sync pattern. In the Ethernet protocol, it should be programmed with 0xD555.
At reset, it defaults to 0x7E7E (two HDLC flags), so it does not need to be written for HDLC
mode. When the DSR is used to send out syncs (such as in transparent mode), the contents
of the DSR are always transmitted LSB first.
16.9.5 Transmit-on-Demand Register
If no frame is currently being transmitted by the serial communication controller, the RISC
microcontroller periodically polls the R bit of the next TX buffer descriptor to see if you have
requested a new frame/buffer to be transmitted. This polling algorithm depends on the serial
communication controller configuration, but occurs every 8 to 32 serial transmit clocks. You
can, however, request that the RISC microcontroller begin processing the new frame/buffer
immediately, without waiting until the normal polling time. To obtain immediate processing,
the TOD bit in the transmit-on-demand register (TODR) is set after the R bit is set in the TX
buffer descriptor.
This feature, which decreases the transmission latency of the transmit buffer/frame, is
particularly useful in LAN-type protocols where maximum interframe GAP times are limited
by the protocol specification. Since the transmit-on-demand feature gives high priority to the
specified TX buffer descriptor, it can conceivably affect the servicing of the receive FIFO.
Therefore, it is recommended that you only use the transmit-on-demand feature when a
high-priority TX buffer descriptor has been prepared and if a sufficient amount of time has
passed since the serial communication controller was transmitted.
DSR
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIELD
SYN2
SYN1
RESET
0111111001111110
R/W
R/W
ADDR
(IMMR & 0xFFF0000) + 0xA2E