
185
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
To enter any of the sleep modes, the SE bit in in the SMCR register (see
"SMCR –instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register
select which sleep mode will be activated by the SLEEP instruction. See chapter
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up.
The MCU is then halted for four cycles in addition to the start-up time, executes the
interrupt routine, and resumes execution from the instruction following SLEEP. The
contents of the Register File and SRAM are unaltered when the device wakes up from
sleep. Note that SRAM data retention must be enabled in some sleep modes to
If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset
Vector.
12.2.1 Idle Mode
When the SM2:0 bits are written to 000 in the SMCR register, the SLEEP instruction
makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART,
Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts clkCPU and
clkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and
Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC
is enabled, a conversion starts automatically when this mode is entered.
12.2.2 ADC Noise Reduction Mode
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode (ADCNRM), stopping the CPU but allowing the ADC, the
external interrupts, 2-wire Serial Interface address match, Timer/Counter2 and the
Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O,
clkCPU, and clkFLASH, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution
measurements. If the ADC is enabled, a conversion starts automatically when this
mode is entered. Apart form the ADC Conversion Complete interrupt, only an External
Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out Reset, a 2-wire
serial interface interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt,
an external level interrupt on INT7:4 or a pin change interrupt can wakeup the MCU
from ADC Noise Reduction mode.
12.2.3 Power-down Mode
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the 16 MHz crystal oscillator is stopped (if selected by
CKSEL fuses), while the external interrupts, the 2-wire Serial Interface, and the
Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset,
a Brown-out Reset, 2-wire Serial Interface address match, an external level interrupt on
INT7:4, an external interrupt on INT3:0, a pin change interrupt, or a symbol counter
interrupt can wake up the MCU. This sleep mode basically halts all generated clocks,
allowing operation of asynchronous modules only.