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42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
The 3 Bit value controls the symbol counter clock prescaler. The input clock to the
prescaler is the 16MHz transceiver clock. The different prescaler values are defined in
the table below. The default prescaler setting is 62.5kHz. If the transceiver clock is
selected, the counter continues on the RTC time base during sleep mode, regardless of
the SCCKDIV setting.
Table 10-83 SCCKDIV Register Bits
Register Bits
Value
Description
SCCKDIV2:0
0
Transceiver Clock divided by 256, (62.5kHz)
1
Transceiver Clock divided by 128, (125kHz)
2
Transceiver Clock divided by 64, (250kHz)
3
Transceiver Clock divided by 32, (500kHz)
4
Transceiver Clock divided by 16, (1MHz)
5
Transceiver Clock divided by 8, (2MHz)
6
Transceiver Clock divided by 4, (4MHz)
Bit 1 – SCEECLK - Enable External Clock Source on PG2
If this bit is set, a asynchronous clock provided on PG2 can be used to run the symbol
counter. SCEECLK overrieds SCCKSEL and forces the selection of the external clock
source. The clock source on PG2 can have a maximum frequency of 1/4 of the
controller clock speed. If selected, the clock on PG2 is used during sleep mode also.
Bit 0 – SCENBO - Backoff Slot Counter enable
If this bit is set, the backoff slot counter starts working. To enable the corresponding
IRQ the SCIRQM register must be updated.
10.11.36 SCSR – Symbol Counter Status Register
Bit
7
6
5
4
3
2
1
0
NA ($DE)
Res6
Res5
Res4
Res3
Res2
Res1
Res0
SCBSY
SCSR
Read/Write
R
Initial Value
0
Bit 7:1 – Res6:0 - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
Bit 0 – SCBSY - Symbol Counter busy
This bit is set if a write operation to the symbol counter register is pending. This bit is
set after writing the counter low byte (SCCNTLL) until the symbol counter is updated
with the new value. This update process can take up to 16 s and during this time no
read or write access to the 32 bit counter register should occur.
10.11.37 SCIRQS – Symbol Counter Interrupt Status Register
Bit
7
6
5
4
3
2
1
0
NA ($E0)
Res2
Res1
Res0
IRQSBO IRQSOF IRQSCP3 IRQSCP2 IRQSCP1
SCIRQS
Read/Write
R
RW
Initial Value
0