
156
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
clock source change is indicated in the bit SCCKSEL of Register
"SCCR0 – Symbolradio transceiver is in SLEEP mode.
After wake up, the counter switches back to the clock source which was selected before
going to sleep mode. Switching the clock source from RTC to 16 MHz resets the 16
MHz clock prescaler. This makes sure, that after switching back the clock source, the
symbol counter starts counting with a full 16 s symbol period.
The clock source can be selected with bit SCCKSEL in the SCCR0 Register
Note: The AVR system clock has to be at least 4 times the symbol counter clock
frequency. The symbol counter clock frequency is usually 62.5kHz, which would require
a minimum of 250kHz AVR system clock frequency.
10.3 32 bit Register Access (Atomic Read/Write)
All 32 bit registers support atomic read or write operation. That means reading or writing
the least significant xxxLL byte (the register name ends in LL) updates or captures the
complete 32 bit value.
Read Access: 1. Reading the LL-Byte captures the 32 bit value in a temporary register
2. Read the upper 3 bytes
Write Access: 1. Write the upper 3 byte
2. Writing the LL-Byte stores the 32 bit value in the counter registers
The same temporary register is used for all 32 bit register of the MAC symbol counter.
10.4 Symbol Counter (32 bit, SCCNT)
The symbol counter is a 32 bit counter which can be sourced by a 62.5 kHz clock,
derived from the 16 MHz system clock or from the RTC (32.768 kHz). If sourced by the
RTC, a special control circuitry ensures that the counter error does not exceed one
symbol period.
The symbol counter can be set or read from the controller. Reading must start with the
least significant byte. If the least significant byte is accessed, all 32 bit of the counter
are captured. A read access to SCCNTLL requires a maximum of three AVR clocks.
Reading the upper three bytes of the counter requires two CPU clock cycles for each
byte.
Writing to the counter should start with the most significant byte. Writing the least
significant byte initiates the counter update and the new 32 bit counter value is loaded
into the counter with the next available counter clock edge. This can take up to 16 s
beginning from the low byte write operation, if the counter is sourced by the RTC.
If the counter clock is derived from the 16 MHz clock system, the new counter value is
stored immediately.
During the counter update cycle, the counter busy flag SCBSY in the SCSR register is
set to “1”. As long as this bit is “1”, no further read/write access to the counter should be
initiated. The same applies if the AVR is forced to any sleep mode with disabled AVR
clock, right after writing to the SCCNT register. If the counter busy flag is not checked
before going to sleep, it is possible that the counter register is not updated correctly.
The symbol counter overflow is indicated by a overflow interrupt. The interrupt is
generated when the counter turns from 0xFFFFFFFF to 0x00000000.
10.5 Symbol Counter SFD Timestamp Register (32 bit, SCTSR, Read Only)
The SFD timestamp register stores the symbol counter value at the time, the SFD has
been detected. The Register value becomes valid if a valid frame length byte (frame