
203
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
Bit 5 – LLDONE - Calibration Done
This bit indicates the last state of the calibration algorithm. The data register contents is
updated with new calibration data after the bit changed to 1. The bit will only be high for
one 64kHz clock period, because a new calibration loop is started automatically.
Bit 4 – LLCOMP - Comparator Output
This bit indicates the output state of the comparator of the low-leakage voltage
regulator. In this way the calibration progress can be directly monitored for debug
purposes. The state of the bit changes at most every 64kHz clock period.
Bit 3 – LLCAL - Calibration Active
This bit indicates that the automatic calibration is in progress. The analog part of the
calibration circuit is powered up if the bit is 1.
Bit 2 – LLTCO - Temperature Coefficient of Current Source
This bit shows the status of the selection of the temperature coefficient. The state of the
bit is updated in the course of the automatic calibration. A valid value is present after
the LLDONE bit is 1 for the first time. Write access is only enabled when the automatic
calibration is turned off (LLENCAL is 0). This bit should not be changed without further
information.
Bit 1 – LLSHORT - Short Lower Calibration Circuit
This bit shows the status of the short switch for the lower calibration circuit. The state of
the bit is updated in the course of the automatic calibration. A valid value is present
after the LLDONE bit is 1 for the first time. If this bit is set to 1 register LLDRL has no
function. Write access is only possible when the automatic calibration is turned off
(LLENCAL is 0). This bit should not be changed without further information.
Bit 0 – LLENCAL - Enable Automatic Calibration
This bit enables the automatic calibration. The automatic calibration runs if the state of
the bit is 1. Write access to the two data register and the bits LLSHORT and LLTCO is
then denied. If the state of LLENCAL is 0 then the calibration algorithm is stopped and
the output voltage of the low-leakage voltage regulator is defined by the values in the
two data register LLDRL and LLDRH and by the bits LLSHORT and LLTCO.
12.6.11 LLDRH – Low Leakage Voltage Regulator Data Register (High-Byte)
Bit
7
6
5
4
3
2
1
0
NA ($131)
Res2
Res1
Res0
LLDRH4 LLDRH3 LLDRH2 LLDRH1 LLDRH0
LLDRH
Read/Write
R
RW
Initial Value
0
The high-byte of the calibration data can be accessed through this register. Write
access is only enabled when the bit LLENCAL of the LLCR register is 0. Then the data
bits LLDRH4:0 directly control the output voltage of the low-leakage voltage regulator.
Higher numbers generate lower voltages. If the bit LLENCAL is 1 then the results of the
automatic calibration are stored.
Bit 7:5 – Res2:0 - Reserved
These bits are reserved for future use.