
215
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
cleared before another reset occurs, the source of the reset can be found by examining
the Reset Flags. Note, after power on the bit EXTRF has to be ignored.
Bit 7:5 – Res2:0 - Reserved
Bit 4 – JTRF - JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset,
or by writing a logic zero to the flag.
Bit 3 – WDRF - Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
Bit 2 – BORF - Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
Bit 1 – EXTRF - External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
Bit 0 – PORF - Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to
the flag.
13.5.2 WDTCSR – Watchdog Timer Control Register
Bit
7
6
5
4
3
2
1
0
NA ($60)
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
WDTCSR
Read/Write
RW
Initial Value
0
Bit 7 – WDIF - Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer
is configured for interrupt. WDIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic
one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out
Interrupt is executed.
Bit 6 – WDIE - Watchdog Timeout Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog
Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog
Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the
Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System
Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the
corresponding interrupt vector will clear WDIE and WDIF automatically by hardware
(the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog
Timer security while using the interrupt. To stay in Interrupt and System Reset Mode,
WDIE must be set after each interrupt. This should however not be done within the
interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out,
a System Reset will be applied.