
500
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the
Flash load operation will abort and the data loaded will be lost.
Bit 3 – BLBSET - Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and
the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared
upon completion of the lock bit set, or if no SPM instruction is executed within four clock
cycles. A LPM instruction within three cycles after BLBSET and SPMEN are set in the
SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the
Z pointer) into the destination register.
Bit 2 – PGWRT - Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles executes page write, with the data stored in the temporary buffer. The
page address is taken from the high part of the Z pointer. The data in R1 and R0 are
ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM
instruction is executed within four clock cycles. The CPU is halted during the entire
page write operation if the NRWW section is addressed.
Bit 1 – PGERS - Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles executes page erase. The page address is taken from the high part of
the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon
completion of a page erase, or if no SPM instruction is executed within four clock
cycles. The CPU is halted during the entire page write operation if the NRWW section is
addressed.
Bit 0 – SPMEN - Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one
together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM
instruction will have a special meaning, see description above. If only SPMEN is written,
the following SPM instruction will store the value in R1:R0 in the temporary page buffer
addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will
auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed
within four clock cycles. During page erase and page write, the SPMEN bit remain high
until the operation is completed. Writing any other combination than "10001", "01001",
"00101", "00011" or "00001" in the lower five bits will have no effect.
30.7.2 NEMCR – Flash Extended-Mode Control-Register
Bit
7
6
5
4
3
2
1
0
NA ($75)
Resx7
ENEAM
AEAM1
AEAM0
Resx3
Resx2
Resx1
Resx0
NEMCR
Read/Write
RW
Initial Value
0
1
0
1
0
The Flash Extended-Mode Control-Register handles the extended address-mode of the
extra rows.
Bit 7 – Resx7 - Reserved
Bit 6 – ENEAM - Enable Extended Address Mode for Extra Rows
When active high, the extended address mode of the extra rows is enabled. The
address is decoded from bits AEAM1:0 of this register.