
452
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
If the user has a fixed voltage source connected to the AREF pin, the user may not use
the other reference voltage options in the application, as they will be shorted to the
external voltage. An external reference voltage must be supplied with a very low
dependent and changes (current steps) in the course of the successive approximation
process. If no external voltage is applied to the AREF pin, the user may switch between
AVDD, 1.5V and 1.6V as reference selection. For internal references a stable voltage is
indicated by the REFOK bit in ADCSRB.
Changes of the reference selection bits REFSn will take effect until a conversion start is
requested by setting ADSC in ADCSRA. After the reference voltage selection is
updated a settling time is required for the reference voltage to stabilize. This settling
phase is automatically inserted by the ADC interface when changing the reference
selection while the ADC is enabled.
Notes:
1. The ADC has to be disabled and enabled again for new reference selections in
ATmegaRF128RFA1.
2. Changing the reference voltage in Free Running mode will abort Free Running
mode. The newly selected reference voltage is available after the automatically
inserted settling phase, yet no new conversion will be started.
27.7 ADC Noise Canceller
The ADC features a noise canceller that enables conversion during sleep mode to
reduce noise induced from the CPU core and other I/O peripherals. The noise canceller
can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the
following procedure should be used:
1. Make sure that the ADC is enabled and is not busy converting. Single Conversion
mode must be selected and the ADC Conversion Complete interrupt must be
enabled.
2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion
once the CPU has been halted.
3. If no other interrupts occur before the A/D conversion completes, the ADC interrupt
will wake up the CPU and execute the ADC Conversion Complete interrupt routine.
If another interrupt wakes up the CPU before the A/D conversion is complete, that
interrupt will be executed, and an ADC Conversion Complete interrupt request will
be generated when the A/D conversion completes. The CPU will remain in active
mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes
than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to
ADEN before entering such sleep modes to avoid excessive power consumption.
27.7.1 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in
Figure 27-11 onpage 453. An analog source applied to ADCn is subjected to the pin capacitance and
input leakage of that pin, regardless of whether that channel is selected as input for the
ADC. When the channel is selected, the source must drive the S/H capacitor through
the series resistance (combined resistance in the input path).
The ADC is optimized for analog signals having output impedance ZOUT of
approximately 3 k or less. If such a source is used, the sampling time will be
negligible. If a source with higher impedance is used, the correct sampling time will