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參數資料
| 型號： | MC56F8323 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 16-bit Hybrid Controller(16位混合控制器) |
| 中文描述： | 16位混合控制器（16位混合控制器） |
| 文件頁數： | 93/132頁 |
| 文件大小： | 2202K |
| 代理商： | MC56F8323 |
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Operation with Security Enabled
56F8323 Technical Data
Preliminary
93
Part 7 Security Features
The 56F8323 offers security features intended to prevent unauthorized users from reading the
contents of the Flash memory (FM) array. The 56F8323’s Flash security consists of several
hardware interlocks that block the means by which an unauthorized user could gain access to the
Flash array.
However, part of the security must lie with the user’s code. An extreme example would be user’s
code that dumps the contents of the internal program, as this code would defeat the purpose of
security. At the same time, the user may also wish to put a “backdoor” in his program. As an
example, the user downloads a security key through the SCI, allowing access to a programming
routine that updates parameters stored in another section of the Flash.
7.1 Operation with Security Enabled
Once the user has programmed the Flash with his application code, the 56F8323 can be secured by
programming the security bytes located in the FM configuration field, which occupies a portion of
the FM array. These non-volatile bytes will keep the part secured through reset and through
power-down of the device. Only two bytes within this field are used to enable or disable security.
Refer to the Flash Memory section in the
56F8300 Peripheral User Manual
for the state of the
security bytes and the resulting state of security. When Flash security mode is enabled in
accordance with the method described in the Flash Memory module specification, the 56F8323
will disable the EOnCE interface, preventing access to internal code. Normal program execurtion
is otherwise unaffected.
7.2 Flash Access Blocking Mechanisms
The 56F8323 has several operating functional and test modes. Effective Flash security must
address operating mode selection and anticipate modes in which the on-chip Flash can be
compromised and read without explicit user permission. Methods to block these are outlined in the
next subsections.
7.2.1
At boot time, the SIM determines in which functional modes the 56F8323 will operate. These are:
Forced Operating Mode Selection
Unsecured Mode
Secure Mode (EOnCE disabled)
When Flash security is enabled as described in the Flash Memory module specification, the
56F8323 will disable the EOnCE debug interface.
7.2.2
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug
interface for the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG
interface onto which the EOnCE port functionality is mapped. When the 56F8323 boots, the chip
level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability and
access to the ID register.
Disabling EOnCE Access
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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相關代理商/技術參數 |
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| MC56F8323EVM | 功能描述:開發(fā)板和工具包 - 其他處理器 MC56F832X Dev Kit RoHS:否 制造商:Freescale Semiconductor 產品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MC56F8323EVM | 制造商:Freescale Semiconductor 功能描述:Tools Development kit Kit Con |
| MC56F8323EVME | 功能描述:開發(fā)板和工具包 - 其他處理器 MC56F8323 EVAL BRD RoHS:否 制造商:Freescale Semiconductor 產品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MC56F8323EVME | 制造商:Freescale Semiconductor 功能描述:Evaluation Kit for MC56F832x and MC56F81 |
| MC56F8323MFB60 | 功能描述:數字信號處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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