參數資料
型號: MC56F8323
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Hybrid Controller(16位混合控制器)
中文描述: 16位混合控制器(16位混合控制器)
文件頁數: 122/132頁
文件大?。?/td> 2202K
代理商: MC56F8323
122
56F8323 Technical Data
Preliminary
A, the internal [static component], is comprised of the DC bias currents for the oscillator, current,
PLL, and voltage references. These sources operate independently of processor state or operating
frequency.
B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
C, the internal [dynamic component], is classic C*V
2
*F CMOS power dissipation corresponding
to the 56800E core and standard cell logic.
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive
loading on the external pins of the chip. This is also commonly described as C*V
2
*F, although
simulations on two of the IO cell types used on the 56800E reveal that the power-versus-load curve
does have a non-zero Y-intercept.
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and
frequency at which the outputs change.
Table 10-25
provides coefficients for calculating power
dissipated in the IO cells as a function of capacitive load. In these cases:
TotalPower
=
Σ
((Intercept + Slope*Cload)*frequency/10MHz)
where:
Summation is performed over all output pins with capacitive loads
TotalPower is expressed in mW
Cload is expressed in pF
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was
found to be fairly low when averaged over a period of time.
E, the external [static component], reflects the effects of placing resistive loads on the outputs of
the device. Sum the total of all V
2
/R or IV to arrive at the resistive load contribution to power.
Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of eight
PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW.
In previous discussions, power consumption due to parasitics associated with pure input pins is
ignored, as it is assumed to be negligible.
Table 10-25 IO Loading Coefficients at 10MHz
Intercept
Slope
8mA CMOS 3-State Output Pad with Input-Enabled Pull-Up
1.3
0.11mW / pF
4mA CMOS 3-State Output Pad with Input-Enabled Pull-Up
1.15mW
0.11mW / pF
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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