參數(shù)資料
型號: MC56F8323
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Hybrid Controller(16位混合控制器)
中文描述: 16位混合控制器(16位混合控制器)
文件頁數(shù): 128/132頁
文件大小: 2202K
代理商: MC56F8323
128
56F8323 Technical Data
Preliminary
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V
DD
and V
SS
circuits.
Take special care to minimize noise levels on the V
REF
, V
DDA
and V
SSA
pins
Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. Designs that do not require
debugging functionality, such as consumer products, should tie these pins together.
Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should
provide an interface to this port to allow in-circuit Flash programming
12.3 Power Distribution and I/O Ring Implementation
Figure 12-1
illustrates the general power control incorporated in the 56F8323. This chip contains
an internal regulator which can be disabled. The regulator takes regulated 3.3V power from the
V
DD_IO
pins and provides 2.5V to the internal logic of the chip. This means the entire part can be
powered from the 3.3V supply.
Notes:
Flash, RAM and internal logic are powered from the core regulator output
All circuitry, analog
and
digital, shares a common V
SS
bus
Figure 12-1 56F8323 Power Management
REG
CORE
V
CAP
I/O
ADC
V
DD
V
SS
OCS
REG
V
DDA_OSC_PLL
ROSC
V
SSA_ADC
V
DDA_ADC
V
REFH
V
REFP
V
REFMID
V
REFN
V
REFLO
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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