參數(shù)資料
型號: MC56F8323
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Hybrid Controller(16位混合控制器)
中文描述: 16位混合控制器(16位混合控制器)
文件頁數(shù): 19/132頁
文件大小: 2202K
代理商: MC56F8323
56F8323 Signal Pins
56F8323 Technical Data
Preliminary
19
PWMA3
(MISO1)
(GPIOA3)
8
Output
Schmitt
Input/
Output
Schmitt
Input/
Output
Tri-Stated
Input
Input
PWMA3
— This is one of six PWMA output pins.
SPI 1 Master In/Slave Out
— This serial data pin is an input
to a master device and an output from a slave device. The
MISO line of a slave device is placed in the high-impedance
state if the slave device is not selected. The slave device
places data on the MISO line a half-cycle before the clock
edge the master device uses to latch the data.
Port A GPIO
— This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is PWMA3.
PWMA4
(MOSI1)
(GPIOA4)
9
Output
Schmitt
Input/
Output
Schmitt
Input/
Output
Tri-Stated
Tri-stated
Input
PWMA4
— This is one of six PWMA output pins.
SPI 1 Master Out/Slave In
— This serial data pin is an output
from a master device and an input to a slave device. The
master device places data on the MOSI line a half-cycle
before the clock edge the slave device uses to latch the data.
Port A GPIO
— This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is PWMA4.
PWMA5
(SCLK1)
(GPIOA5)
10
Output
Schmitt
Input/
Output
Schmitt
Input/
Output
Tri-Stated
Input
Input
PWMA5
— This is one of six PWMA output pins.
SPI 1 Serial Clock
— In the master mode, this pin serves as
an output, clocking slaved listeners. In slave mode, this pin
serves as the data clock input. A Schmitt trigger input is used
for noise immunity.
Port A GPIO
— This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is PWMA5.
FAULTA0
(GPIOA6)
13
Schmitt
Input
Schmitt
Input/
Output
Input
Input
FAULTA0
— This fault input pin is used for disabling selected
PWMA outputs in cases where fault conditions originate
off-chip.
Port A GPIO
— This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is FaultA0.
Table 2-2 56F8323 Signal and Package Information for the 64-Pin LQFP
Signal Name
Pin No.
Type
State During
Reset
Signal Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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