參數(shù)資料
型號(hào): MC56F8323
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Hybrid Controller(16位混合控制器)
中文描述: 16位混合控制器(16位混合控制器)
文件頁數(shù): 56/132頁
文件大?。?/td> 2202K
代理商: MC56F8323
56
56F8323 Technical Data
Preliminary
5.6.1
Interrupt Priority Register 0 (IPR0)
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 15–14
5.6.1.2
EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)—
Bits13–12
This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.3
EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 9–0
5.6.2
Interrupt Priority Register 1 (IPR1)
Figure 5-4 Interrupt Priority Register 1 (IPR1)
5.6.2.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 15–6
Base + $0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
BKPT_U0 IPL
STPCNT IPL
0
0
0
0
0
0
0
0
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Base + $1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
0
0
0
RX_REG IPL
TX_REG IPL
TRBUF IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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