參數(shù)資料
型號: MC56F8323
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Hybrid Controller(16位混合控制器)
中文描述: 16位混合控制器(16位混合控制器)
文件頁數(shù): 27/132頁
文件大小: 2202K
代理商: MC56F8323
Interrupt Vector Table
56F8323 Technical Data
Preliminary
27
4.3 Interrupt Vector Table
Table 4-3
provides the 56F8323’s reset and interrupt priority structure, including on-chip
peripherals. The table is organized with higher-priority vectors at the top and lower-priority
interrupts lower in the table. As indicated, the priority of an interrupt can be assigned to different
levels, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before
level 2, and so on. For a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see
Section 5.6.11
for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1
of the interrupt vector table. In these instances, the first two locations in the vector table must
contain branch or JMP instructions. All other entries must contain JSR
instructions.
Table 4-2 Program Memory Map at Reset
Begin/End Address
Memory Allocation
P: $1F FFFF
P: $03 0000
RESERVED
P: $02 FFFF
P: $02 F800
On-Chip Program RAM
4KB
P: $02 F7FF
P: $02 1000
RESERVED
P: $02 0FFF
P: $02 0000
Boot Flash
8KB
Cop Reset Address = $02 0002
Boot Location = $02 0000
P: $01 FFFF
P: $00 4000
RESERVED
P: $00 3FFF
P: $00 0000
Internal Program Flash
32KB
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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