參數(shù)資料
型號(hào): MC56F8323
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Hybrid Controller(16位混合控制器)
中文描述: 16位混合控制器(16位混合控制器)
文件頁數(shù): 22/132頁
文件大小: 2202K
代理商: MC56F8323
22
56F8323 Technical Data
Preliminary
TC1
(RXD0)
(GPIOC5)
64
Schmitt
Input/
Output
Schmitt
Input
Schmitt
Input/
Output
Input
Input
Input
TC1
— Timer C, Channel 1
Receive Data
— SCI0 receive data input
Port C GPIO
— This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is TC1.
TC3
(GPIOC4)
63
Schmitt
Input/
Output
Schmitt
Input/
Output
Input
Input
TC1
— Timer C Channel 3
Port C GPIO
— This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is TC3.
IRQA
V
PP
12
Schmitt
Input
Input
Input
N/A
External Interrupt Request A
— The IRQA input is an
asynchronous external interrupt request during Stop and Wait
mode operation. During other operating modes, it is a
synchronized external interrupt request which indicates an
external device is requesting service. It can be programmed
to be level-sensitive or negative-edge-triggered
V
PP
— This pin is used for Flash debugging purposes.
RESET
2
Schmitt
Input
Input
Reset
— This input is a direct hardware reset on the
processor. When RESET is asserted low, the device is
initialized and placed in the reset state. A Schmitt trigger input
is used for noise immunity. The internal reset signal will be
deasserted synchronous with the internal clocks after a fixed
number of internal clocks.
To ensure complete hardware reset, RESET and TRST
should be asserted together. The only exception occurs in a
debugging environment when a hardware device reset is
required and the JTAG/EOnCE module must not be reset. In
this case, assert RESET, but do not assert TRST.
Table 2-2 56F8323 Signal and Package Information for the 64-Pin LQFP
Signal Name
Pin No.
Type
State During
Reset
Signal Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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