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| 型號(hào)： | M66596WG |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 0.80 MM PITCH, FBGA-64 |
| 文件頁(yè)數(shù)： | 91/133頁(yè) |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 58 of 127
3.1.8.4 Stopping the internal clock supply (From a normal operating state to clock stop state)
The timing diagram of the transition from the normal operation state to the clock stop state of the controller is
shown in Figure 3.8. The transitions should be operated according to the following sequence.
(1) Software disables the internal clock suppliance.
"SCKE=0"
(2) Software waits until an internal clock stops.
(A waiting time of at least 300 ns is necessary.)
(3) Software disables the PLL.
"PLLC=0"
(4) Software waits for the PLL to stop.
(A waiting time of at least 300 ns is necessary.)
(5) Software disables reference clock suppliance.
"RCKE=0"
(6) Software waits until the reference clock stops.
(A waiting time of at least 300 ns is necessary.)
(7) Software disables the oscillation buffer.
"XCKE=0"
XCKE
RCKE
PLLC
SCKE
(2) min 300ns
(1)
Start of transit to
the clock stop
(3)
(5)
(4) min 300ns
(6) min 300ns
(7)
Figure 3.8 Transition control timing to the clock stop state
3.1.8.5 Starting the internal clock supply (From the clock stop state to the normal operating state: with
"ATCKM=1")
The timing diagram from the clock stop state to the normal operation state is shown in Figure 3.9. The timing
diagram is in the case of the auto clock supply function is enabled ("ATCKM=1"; recommended setting).
In this case, the controller operates registers when resume signal is detected. The controller changes to the normal
operation state by waiting for access prohibition time after resume interruption is generated. The register operation
by software is not required. If VBUS interrupt is occurs, the softwear need to enable the oscillation buffer
(1) The controller detects the resume signal or VBUS changes on a USB bus, and the INT_N pin is asserted.
(2) When resume signal is received, the controller automatically enables the oscillation buffer. "XCKE=1(H/W)"
When VBUS change occurs, the softwear needs to enable the oscillation buffer. "XCKE=1.
(3) The softwear waits until access is enabled. (A waiting time of at least 2.5 ms is necessary.)
(4) The controller automatically enables RCKE, PLLC, and SCKE during (3).
(5) Software performs resume processing depending on the interrupt factor, resume or attachment.
XCKE
Resume :H/W
VBUS chage :S/W
RCKE(H/W)
PLLC(H/W)
SCKE(H/W)
(3) 2.5ms (access disabled)
Clock stop
recovery
INT_N
Event
CS_N
(1),(2)
(4)
(5)
Figure 3.9 Recovery control timing from the clock stop state with “ATCKM=1”
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