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參數(shù)資料
| 型號(hào)： | M66596WG |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 0.80 MM PITCH, FBGA-64 |
| 文件頁(yè)數(shù)： | 103/133頁(yè) |
| 文件大?。?/td> | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 69 of 127
3.2.7
Control transfer stage transition interrupt
Figure 3.17 shows a diagram of how the controller handles the control transfer stage transition. In the Peripheral
mode, the controller controls the control transfer sequence and generates control transfer stage transition interrupts.
Control transfer stage transition interrupts can be enabled or disabled individually, using the INTENB0 register.
Also, the transfer stage that underwent a transition can be confirmed using the CTSQ bit of the INTSTS0 register.
The control transfer sequence errors are noted below. If an error occurs, the PID bit of the DCPCTR register goes to
“1X” (STALL).
(1)
During control read transfers
(a) At the IN token of the data stage, an OUT or PING token is received when there have been no data
transfers at all
(b) An IN token is received at the status stage
(c)
A packet is received at the status stage for which the data packet is "DATAPID=DATA0”
(2)
During control write transfers
(a) For the OUT token of the data stage, when there have been no ACK responses at all, the IN token is
received
(b) A packet is received at the data stage for which the first data packet is "DATAPID=DATA0"
(c)
At the status stage, an OUT or PING token is received
(3)
During control write no-data transfers
(a) At the status stage, an OUT or PING token is received
At the control write transfer stage, if the number of received data elements exceeds the wLength value of the USB
request, it cannot be recognized as a control transfer sequence error. Also, at the control read transfer status stage,
packets other than Zero-Length packets are received by an ACK response being carried out, and the transfer ends
normally.
If a CTRT interrupt occurs in response to a sequence error (“SERR=1”), the “CTSQ=110” value is held until
“CTRT=0” is written from the user system (the interrupt status is cleared). Because of this, while “CTSQ=110” is
being held, the CTRT interrupt that ends the setup stage will not be generated even if a new USB request is received.
(The controller holds the setup stage end, and after the interrupt status has been cleared by software, a setup stage
end interrupt is generated.)
ACK sent
ACK received
Error detected
Setup token
received
ACK sent
“CTSQ=011”
Control write data
stage
“CTSQ=100”
Control write status
stage
“CTSQ=000”
Idle stage
“CTSQ=101”
Control write
no-data status stage
OUT token
IN token
ACK received
1
3
4
“CTSQ=000”
Setup stage
“CTSQ=001”
Control read data
stage
“CTSQ=010”
Control read status
stage
2
1
4
“CTSQ=110”
Control transfer
sequence error
5
CTRT interrupts
1. Setup stage completed
2. Control read transfer status stage transition
3. Control write transfer status stage transition
4. Control transfer completed
5. Control transfer sequence error
Setup token received
If errors are detected at all stages in
the box, IN token reception is valid.
ACK sent
Figure 3.17 Control transfer stage transitions
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