- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄45052 > M66596WG UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 PDF資料下載
參數(shù)資料
| 型號(hào)： | M66596WG |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 0.80 MM PITCH, FBGA-64 |
| 文件頁(yè)數(shù)： | 80/133頁(yè) |
| 文件大?。?/td> | 1611K |
| 代理商： | M66596WG |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)當(dāng)前第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
M66596FP/WG
rev .1.00
2006.3.14
page 48 of 127
PIPE1 control register [PIPE1CTR]
<Address: 70H>
PIPE2 control register [PIPE2CTR]
<Address: 72H>
PIPE3 control register [PIPE3CTR]
<Address: 74H>
PIPE4 control register [PIPE4CTR]
<Address: 76H>
PIPE5 control register [PIPE5CTR]
<Address: 78H>
PIPE6 control register [PIPE6CTR]
<Address: 7AH>
PIPE7 control register [PIPE7CTR]
<Address: 7CH>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BSTS INBUFM
ACLRM SQCLR SQSET SQMON
PID
0
-
0
-
0
?
0
-
0
-
0
-
0
-
0
?
0
Bit
Name
Function
S/W
H/W
Note
15
BSTS
Buffer Status
0: Buffer access is disabled.
1: Buffer access is enabled.
R
W
14
INBUFM
Sending buffer status monitor
0: No data which can be transmitted in a buffer
1: The data which can be transmitted is in a buffer
memory.
R
W
13-10 Nothing is placed here. These should be fixed at “0”.
9
ACLRM
Auto Buffer Clear mode
0: Disabled
1: Enabled (all buffers are initialized)
R(0)/
W(1)
R/W(0) 3.4.1.4
8
SQCLR
Toggle Bit Clear
0: Invalid
1: Specifies DATA0
R(0)/
W(1)
R
7
SQSET
Toggle Bit Set
0: Invalid
1: Specifies DATA1
R(0)/
W(1)
R
6
SQMON
Toggle Bit Confirm
0: DATA0
1: DATA1
R
W
1-0 PID
Response PID
00: NAK response
01: BUF response (in keeping with the buffer state)
10: STALL response
11: STALL response
R/W
<<Notes>>
*12) The direction of buffer access, writing or reading, is depend on setting of the DIR bit of the PIPECFG register.
*13) The INBUFM bit is valid when softwware sets the DIR bit to Sending-direction.
*14) The INBUFM bit is valid for PIPE1-5.
*15) Software should not set “ACLRM=1” for the PIPE whith selected by the CURPIPE bit of the CFIFOSEL,
DxFIFOSEL
register. After "ACLRM=1", when setting up "ACLRM=0", Software need to wait at lease 100ns.
*16) If the SQCLR bits and the SQSET bits of the DCPCTR register and the PIPExCTR registers are being used to
change the data PID sequence toggle bit for several pipes in succession, an access cycle of at least 200 ns is
required.
*17) The SQCLR bit and SQSET bit should not both be set to “1” at the same time. Before operating either bit,
“PID=NAK” should be set.
*18) The operation is as follows, when setting up PID=BUF.
Host mode and the transmitting direction (OUT).
A transaction is issued when there is transmitting data in a buffer.
A transaction is not issued when there is no transmitting data in a buffer.
Host mode and the receiving direction (IN).
A transaction is issued when there is no receiving data in a buffer.
A transaction is not issued when there is receiving data in a buffer.
Peripheral mode and the transmitting direction (OUT).
A ACK response and receiving a data , when there is no receiving data in a buffer.
A NAK response is carried out to a token, when there is a receiving data in a buffer.
Peripheral mode and the receiving direction (IN).
A Data is transmitted to a IN token.
A NAK response is carried out to a IN token, when there is a transmitting data in a buffer.
And at the time of occurring of a transmission error etc., PID bits are set up by the controller and transmission
is ended.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M6XXLFXI | OTHER CLOCK GENERATOR, QCC16 |
| M300LFXIT | 50 MHz, OTHER CLOCK GENERATOR, QCC16 |
| M74HC00C1R | HC/UH SERIES, QUAD 2-INPUT NAND GATE, PQCC20 |
| M74HC157B1N | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16 |
| M74HC158C1 | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PQCC20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
| M6668 | 制造商:Tamura Corporation of America 功能描述: |
| M66700P | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66700WP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66701P | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。