參數(shù)資料
型號(hào)： M66596WG
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 0.80 MM PITCH, FBGA-64
文件頁(yè)數(shù)： 66/133頁(yè)
文件大?。?/td> 1611K
代理商： M66596WG
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M66596FP/WG
rev .1.00
2006.3.14
page 36 of 127
Interrupt status register 1[INTSTS1]
<Address: 42H>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BCHG
SOFR
DTCH
BEMP
NRDY
BRDY
SIGN
SACK
?
0
-
0
-
0
-
0
?
0
-
0
-
0
-
0
?
0
-
0
-
0
?
Bit
Name
Function
S/W
H/W
Note
15 Nothing is placed here. These should be fixed at “0”.
14 BCHG
USB bus change interrupt status
0: BCHG Interrupts not issued
1: BCHG Interrupts issued
R/W
W
13 SOFR
Frame number refresh interrupt status
This bit is a mirror bit of a 40H SOFR bit.
0: SOF Interrupts not issued
1: SOF Interrupts issued
R/W(0)
W
2.9.1
12 DTCH
Full-Speed detach detect interrupt status
0: DTCH Interrupts not issued
1: DTCH Interrupts issued
R/W
W
11 Nothing is placed here. This should be fixed at “0”.
10 BEMP
Buffer Empty interrupt status
This bit is a mirror bit of a 40H BEMP bit.
0: BEMP interrupts not issued
1: BEMP interrupts issued
R
W
2.9.1
9
NRDY
Buffer Not Ready response interrupt
status
This bit is a mirror bit of a 40H NRDY bit.
0: NRDY interrupts not issued
1: NRDY interrupts issued
R
W
2.9.1
8
BRDY
Buffer Ready interrupt status
This bit is a mirror bit of a 40H BRDY bit.
0: BRDY interrupts not issued
1: BRDY interrupts issued
R
W
2.9.1
7-6 Nothing is placed here. This should be fixed at “0”.
5
SIGN
Setup transaction error detect interrupt
status
0: SIGN interrupts not issued
1: SIGN interrupts issued
R/W
R
4
SACK
Setup transaction complete interrupt
status
0: SACK interrupts not issued
1: SACK interrupts issued
R/W
R
3-0 Nothing is placed here. This should be fixed at “0”.
<<Notes>>
*4) DTCH, SIGN, SACK bit are effective only at the time of a Host mode.
*5) The DTCH bit is effective only at the time of Full-Speed mode.
Please perform detach detection by S/W, such as detecting ignore packet from peripheral device at the time of
Hi-Speed mode.
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