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| 型號(hào)： | M66596WG |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 0.80 MM PITCH, FBGA-64 |
| 文件頁(yè)數(shù)： | 41/133頁(yè) |
| 文件大?。?/td> | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 13 of 127
2 Registers
Reading the table of registers
Bit no.
Each register is connected to a 16-bit internal bus.
Odd-numbered addresses will use b15 to b8, and even-numbered addresses b7 to b0.
Status after reset
This indicates the default state of the register immediately after a reset operation, and after
recovering from the low-power sleep state.
H/W Reset is the default state when an external reset signal has been input from the RST_N
pin.
S/W Reset is the default state when the user system has carried out a bit operation using the
USBE bit.
USB Reset is the default state when the controller has detected a USB bus reset.
Low-power Sleep is the default state when the controller has recovered from the low-power
sleep state.
Items that require particular attention during a reset operation are noted under “ Notes”.
“-“ indicates a state in which there is no operation by the controller, and the user setting is
retained.
“?” indicates that a value is undecided.
S/W Access Condition
This is the condition in effect if the softwear is accessing a register.
H/W Access Condition This is the condition in effect if the controller is accessing a register during any operation
other than a reset.
R ...... Read Only
W ...... Write Only
R/W ...... Read / Write
R(0) ...... "0"Read Only
W(1) ...... "1"Write Only
Note
This is the number of detailed explanations and the number of notes.
Bit Name
This indicates the bit symbol and bit name.
Function Description
This describes active items and notes.
<Example of table notation>
Nothing is placed in shaded sections. These should be fixed at “0”.
Bit number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit symbol
A bit B bit C bit
H/W reset
?
0
S/W reset
?
0
-
USB reset
?
0
-
Low-power sleep state
?
0
Bit
Name
Function
S/W
H/W
Note
15
Nothing is placed here. It should be fixed at “0”.
14
A bit
AAA enabled
0 : Operation disabled
1 : Operation enabled
R/W
R
2.3.1
*1
13
B bit
BBB operation
0 : "L"output
1 : "H"output
R
W
2.3.2
*1
12
C bit
CCC control
0 : .......
1 : .......
R(0)/
W(1)
R
2.3.2
<<Note>>
*1) If the A bit and B bit are being accessed in succession for writing, an access cycle of 300 ns is necessary.
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