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參數(shù)資料
| 型號(hào)： | M66596WG |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 0.80 MM PITCH, FBGA-64 |
| 文件頁(yè)數(shù)： | 51/133頁(yè) |
| 文件大小： | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 22 of 127
2.4.1
USB data bus control
Each bit of the DVSTCTR register can be used to control and confirm the state of the USB data bus based on
the user system.
(a) Remote wakeup (Peripheral mode)
The WKUP bit handles control of remote wakeup signal output to the USB bus. The controller controls the
output time for remote wakeup signals. 2ms after a software has set “1” for the WKUP bit, the M66596 outputs a
10 ms “K-State” then it transfers the bus state to idle. When the bus state is transferred to the idle state, the
controller sets “WKUP=0”.
According to the USB specification, USB idle state must be kept longer than 5ms. Thus if the software set
“WKUP=1” right after detection of Suspend state, the controller will assert “K-State” after 2ms.
(b) Remote wakeup, Resume (Host mode)
A resume signal is output on a USB bus by setting a RESUME bit as 1.
Moreover, when the RWUPE bit is set as 1 and a remote wakeup signal is detected, a resume signal is
outputted to a down port. At this time, a controller sets 1 as a "RESUME" bit. In both cases manage the output
time of a resume signal by S/W. The output of a resume signal is stopped by "RWUP=0" or "RESUME=0" writing
by S/W.
(c)
USB Communication enable (Host mode)
A SOF (or uSOF) packet is transmitted on a USB bus by a UACT bit. The controller manages a SOF packet
interval. When "1" is set as a UACT bitthe SOF packet is sent out. When "0" is set as a UACT bit, after sending
out the next SOF, the controller is made into a bus idle state.
(d) USB bus reset (Host mode)
A USB bus reset signal is outputted by setting a USBRST bit as 1. Software should manage USB bus reset
time. Please set "USBRST=0" after waiting for USB bus reset time.
2.4.2
Communication speed discrimination
If the HSE bit of a SYSCFG register is set as 1, at the time of transmission and reception of USB bus reset,
this controller execute a reset handshake automatically and determine transmission speed. Softwear is able to
confirm the USB speed, using the RHST bit.
If Hi-Speed operation has been set to the disabled state (“HSE=0”) by softwere, the controller immediately
establishes Full-Speed operation (“RHST=10”), without executing the reset handshake protocol.
In the Host mode, it is the following timing that a result is reflected in a RHST bit after USB reset is desabled.
Software needs to wait connected peripheral is Full-Speed device.
- Full-Speed device : When a USB bus changes from the SE0 State to J State by with USB bus reset.
- Hi-Speed device : When termination resistance is changed to Hi-Speed mode by the reset handshake.
(It decides during USB bus reset)
After the USB bus reset end (after URST=0 setup), when RHST is not decided after sufficient waiting time,
the USB cable may be disconnect during USB bus reset. In such a case, please check the state of a USB bus by
the LNST bit.
2.4.3
Test mode
Table 2.6 shows the test mode operation of the controller. The UTST bit of the TESTMODE register controls
the USB test signal output during Hi-Speed operation.
Table 2.6 Test mode operation
UTST bit setting
Test mode
Peripheral mode
Host mode
Normal operation
0000
Test_J
0001
1001
Test_K
0010
1010
Test_SE0_NAK
0011
1011
Test_Packet
0100
1100
Reserved
0101-0111
1101-0111
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