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| 型號(hào)： | M66596WG |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 0.80 MM PITCH, FBGA-64 |
| 文件頁(yè)數(shù)： | 35/133頁(yè) |
| 文件大?。?/td> | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 11 of 127
1.7.4
USB data transfers
The controller is capable of all types of transfers: USB communication control transfers, bulk transfers, and
interrupt transfers, as well as isochronous data transfers. The pipes noted below can be used with data transfers
for various types of communication.
(1) Dedicated control transfer pipe(Default Control Pipe(DCP))
(2) Two dedicated interrupt transfer pipes(Pipe6,7)
(3) Three dedicated bulk transfer pipes(Pipe3, 4, 5)
(4) Two pipes for which bulk transfers or isochronous transfers can be selected(Pipe1, 2)
The settings necessary for USB transfers, such as the transfer type, end point number, and maximum packet
size, should be set for each pipe, in conjunction with the user system.
Also, the controller has a built-in 5 kB buffer memory. For a dedicated bulk transfer pipe and the pipes for
which bulk transfers or isochronous transfers can be selected, settings such as the buffer memory assignment
and buffer operation mode which are based on the user system should be entered. The buffer operation mode
setting can be set to enable high-speed data transfers with few interrupts, using the double-buffer configuration
and data packet continuous transfer function.
Access to the buffer memory from the control CPU of the user’s system and the DMA controller is done
through the three FIFO port registers.
1.7.5
DMA interface
The DMA (Direct Memory Access) interface consists of data transfers between the user system and the
controller using the DxFIFO port, and is a type of data transfer in which the CPU is not involved. The controller
is equipped with a 2-channel DMA interface and has the following functions.
(1) A transfer end notification function using the Transfer End signal (DEND signal)
(2) An auto-clear function activated when a Zero-Length packet is received
(3) A “send addition” function used to send a Zero-Length packet based on input of the Transfer End signal
(DEND signal)
(4) A transfer end function using a transaction counter function
The controller supports the two types of DMA interfaces noted below.
(5) Cycle steal transfer
With this type of transfer, the DREQ pin is repeatedly asserted and negated each time a data transfer (1 byte /
1 word) is carried out.
(6) Burst transfer
With this type of transfer, the DREQ pin remains asserted for the pipe buffer area assigned to the pertinent
FIFO port, or until the transfer is ended by the DEND signal, without ever being negated.
Also, the following can be selected as the DMA interface handshake signal (pin): CS_N, RD_N, or WR_N, or
DACK_N. With DMA transfers using a split bus, high-speed DMA transfers are possible by changing the data
setup timing, by operating the OBUS bit of the DMAxCFG register.
1.7.6
SOF pulse output function
An SOF pulse output function is provided that notifies the system of the timing at which SOF packets are
transmited or received.
In the Host mode, when the controller transmits a SOF packet, the controller outputs pulses to an SOF_N pin.
In the Peripheral mode, when the controller recives SOF packet, the controller outputs pulse. And the
controller outputs pulses at fairly regular intervals, using an SOF interpolation timer, even if an SOF packet is
damaged. In the Peripheral mode, it is also possible to output the pulse only when an SOF packet is damaged.
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