- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄45052 > M66596WG UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 PDF資料下載
參數(shù)資料
| 型號(hào)： | M66596WG |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 0.80 MM PITCH, FBGA-64 |
| 文件頁(yè)數(shù)： | 110/133頁(yè) |
| 文件大?。?/td> | 1611K |
| 代理商： | M66596WG |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)當(dāng)前第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
M66596FP/WG
rev .1.00
2006.3.14
page 76 of 127
3.4 Buffer memory
This chapter explains operation about the buffer memory which this controller contains. When there is no
description, both a Host and Peripheral are the same operation.
3.4.1
Buffer memory allocation
Figure 3.19 shows an example of a buffer memory map for the controller. The buffer memory is an area shared by
the user system control CPU and the controller. In the buffer memory status, there are times when the access right
to the buffer memory is allocated to the user system (CPU side), and times when it is allocated to the controller (SIE
side).
The buffer memory sets independent areas for each pipe. In the memory areas, 64 bytes comprise one block, and
the memory areas are set using the first block number of the number of blocks (specified using the BUFNMB and
BUFSIZE
bits of the PIPEBUF register). Moreover, three FIFO ports are used for access to the buffer memory
(reading and writing data). A pipe is assigned to the FIFO port by specifying the pipe number using the CURPIPE
bit of the C/DxFIFOSEL register.
The buffer statuses of the various pipes can be confirmed using the BSTS bit of the DCPCTR register and
PIPExCTR
register. Also, the access right of the FIFO port can be confirmed using the FRDY bit of the C/DxFIFOCTR
register.
FIFO Port
D0FIFO Port
BUFNMB=0, BUFSIZE=3
CFIFO Port
D1FIFO Port
CURPIPE=1
CURPIPE=3
Buffer memory
PIPEBUF reg
PIPE0
PIPE6
PIPE7
PIPE5
PIPE1
PIPE2
PIPE3
PIPE4
BUFNMB=4, BUFSIZE=0
BUFNMB=5, BUFSIZE=0
BUFNMB=6, BUFSIZE=3
BUFNMB=10, BUFSIZE=7
BUFNMB=18, BUFSIZE=3
BUFNMB=22, BUFSIZE=7
BUFNMB=28, BUFSIZE=2
CURPIPE=6
Figure 3.19 Example of buffer memory map
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M6XXLFXI | OTHER CLOCK GENERATOR, QCC16 |
| M300LFXIT | 50 MHz, OTHER CLOCK GENERATOR, QCC16 |
| M74HC00C1R | HC/UH SERIES, QUAD 2-INPUT NAND GATE, PQCC20 |
| M74HC157B1N | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16 |
| M74HC158C1 | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PQCC20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
| M6668 | 制造商:Tamura Corporation of America 功能描述: |
| M66700P | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66700WP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66701P | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。