- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45052 > M66596WG UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 PDF資料下載
參數(shù)資料
| 型號： | M66596WG |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 0.80 MM PITCH, FBGA-64 |
| 文件頁數(shù)： | 82/133頁 |
| 文件大?。?/td> | 1611K |
| 代理商： | M66596WG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁當(dāng)前第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁
M66596FP/WG
rev .1.00
2006.3.14
page 50 of 127
3.1.5
USB data bus resistor control
Figure 3.1 shows a diagram of the connections between the controller and the USB connectors.
For the Peripheral mode, the controller has a built-in pull-up resistor for the D+ signal. “1” should be set for the
DPRPU
bit of the SYSCFG register, then the D+ line is pulled up. The pull-up power supply is AFE33V.
For the Host mode, the controller has a built-in pull-down resistor for the D+ and D- signals. “1” should be set for
the DPRPD bit of the SYSCFG register, then the D+ and D- lines are pulled down.
Also, the controller has a built-in terminal resistor for use when the D+ and D- signals are operating at Hi-Speed,
and a built-in output resistor for Full-Speed operation. The controller automatically switches the built-in resistor
after connection with the PC, by means of reset handshake, suspended state and resume detection. If a disconnection
from the PC is detected, the H/W should be initialized by means of an S/W reset (USBE=0).
If “0” is set for the DPRPU bit of the SYSCFG register in the Peripheral mode, the pull-up resistor (or the terminal
resistor) of the USB data line is disabled, making it possible to notify the host controller of the device disconnection.
M66596
VBUS
USB connector
1
3
2
4 GND
D-
D+
Vbus
DM
DP
RERFIN
5.6K
Impedance control has to be taken into
consideration when designing the D+
and D- lines.
+5V
(at the Host mode)
Figure 3.1 UBS connector connections
3.1.6
Clock supply control
Figure 3.2 shows a block diagram of the controller clock control. Frequency of the input clock for the XIN pin
should be selected using the XTAL bit of the SYSCFG register, while the oscillation buffer is enabled using the XCKE
bit and the clock supply is controlled using the RCKE, PLLC, and SCKE bits. For information on the register control
timing, please refer to 3.1.8, State transition timing.
Auto clock supply
Low-power
control
Input
clock
Oscillation
buffer
XCKE
(bit13)
PLLC, SCKE
(bit11, bit10)
Internal
clock
PLL
Clock control unit
RCKE
(bit12)
Divider
circuit
PCUT
(bit1)
ATCKM
(bit8)
Figure 3.2 Clock control block
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M6XXLFXI | OTHER CLOCK GENERATOR, QCC16 |
| M300LFXIT | 50 MHz, OTHER CLOCK GENERATOR, QCC16 |
| M74HC00C1R | HC/UH SERIES, QUAD 2-INPUT NAND GATE, PQCC20 |
| M74HC157B1N | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16 |
| M74HC158C1 | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PQCC20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
| M6668 | 制造商:Tamura Corporation of America 功能描述: |
| M66700P | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66700WP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
| M66701P | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。