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參數(shù)資料
| 型號： | M66596WG |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 0.80 MM PITCH, FBGA-64 |
| 文件頁數(shù)： | 116/133頁 |
| 文件大?。?/td> | 1611K |
| 代理商： | M66596WG |
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M66596FP/WG
rev .1.00
2006.3.14
page 81 of 127
3.4.2.2 REW bit
It is possible to temporarily stop access to the pipe currently being accessed, access a different pipe, and then
continue processing using the current pipe once again. The REW bit of the C/DxFIFOSEL register is used for
this.
If a pipe is selected when the REW bit is set to “1” and at the same time the CURPIPE bit of the C/DxFIFOSEL
register is set, the pointer used for reading from and writing to the buffer memory is reset, and reading or
writing can be carried out from the first byte. Also, if a pipe is selected with “0” set for the REW bit, data can be
read and written in continuation of the previous selection, without the pointer used for reading from and writing
to the buffer memory being reset.
To access the FIFO port, “FRDY=1” must be confirmed after selecting a pipe.
3.4.2.3 Reading the buffer memory on the SIE side (CFIFO port reading direction)
Even in the “FRDY=0” state, when data cannot be read from the buffer memory, confirming the SBUSY bit in
the CFIFOSIE register and setting “1” for the TGL bit makes it possible for the controller to read and access data
on the SIE side. “PID=NAK” should be set and “SBUSY=0” confirmed, and then “TGL=1” written. The controller
is then able to read data from the CFIFO register. This function can be used only in the buffer memory reading
direction. Also, the BRDY interrupt is generated by operation of the TGL bit.
“1” should not be written for the TGL bit in the following circumstances.
-
When DCP is selected
-
While the buffer memory is being read
-
Pipes in the buffer memory writing direction
3.4.2.4 Clearing the buffer memory on the SIE side (CFIFO port writing direction)
The controller can cancel data that is waiting to be sent, by confirming the SBUSY bit of the CFIFOSIE
register and setting “1” for the SCLR bit.
“PID=NAK” should be set and “SBUSY=0” confirmed, and then “SCLR=1” written. The controller is then able
to write new data from the CFIFO register. This function can be used only in the buffer memory writing direction.
Also, the BRDY interrupt is generated by operation of the SCLR bit.
“1” should not be written for the SCLR bit in the following circumstances.
-
When DCP is selected
-
While data is being written to the buffer memory
-
Pipes in the buffer memory reading direction
3.4.2.5 Transaction counter (DxFIFO port reading direction)
When the specified number of transactions have been completed in the data packet receiving direction, the
controller is able to recognize that the transfer has ended. The transaction counter is a function that operates
when the pipe selected by means of the DxFIFO port has been set in the direction of reading data from the buffer
memory. The transaction counter has a TRNCNT register that specifies the number of transactions and a
current counter that counts the transactions internally. When the current counter matches the number of
transactions specified in the TRNCNT register, reading is enabled for the buffer memory. The current counter of
the transaction counter function is initialized by the TRCLR bit, so that the transactions can be counted again
starting from the beginning. The information read by the TRNCNT register differs depending on the setting of
the TRENB bit.
TRENB=0: The set transaction counter value can be read.
TRENB=1: The value of the current counter that counts the transactions internally can be read.
The conditions for changing the CURPIPE bit are as noted below.
a)
The CURPIPE bit should not be changed until the transaction for the specified pipe has ended.
b)
The CURPIPE bit cannot be changed if the current counter has not been cleared.
The operation conditions for the TRCLR bit are as noted below.
a)
If the transactions are being counted and “PID=BUF”, the current counter cannot be cleared.
b)
If there is any data left in the buffer, the current counter cannot be cleared.
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