參數(shù)資料
型號(hào)： M66596WG
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 0.80 MM PITCH, FBGA-64
文件頁(yè)數(shù)： 58/133頁(yè)
文件大?。?/td> 1611K
代理商： M66596WG
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)當(dāng)前第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
M66596FP/WG
rev .1.00
2006.3.14
page 28 of 127
CFIFO port control register [CFIFOCTR]
<Address: 20H>
D0FIFO port control register [D0FIFOCTR]
<Address: 26H>
D1FIFO port control register [D1FIFOCTR]
<Address: 2CH>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BVAL
BCLR
FRDY
DTLN
0
-
0
-
0
-
0
?
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
Bit
Name
Function
S/W
H/W
Note
15 BVAL
Buffer Memory Valid flag
0: Invalid
1: Writing ended
R/ W(1) R/W
14 BCLR
CPU Buffer Clear
0: Invalid
1: Clears the buffer memory on the CPU side.
R(0)/
W(1)
R/W(0) 3.4.2
13 FRDY
FIFO Port Ready
0: FIFO port access is disabled.
1: The FIFO port can be accessed.
R
W
12 Nothing is placed here. This should be fixed at “0”.
11-0 DTLN
Reception Data Length
The length of the reception data can be
confirmed.
R
W
<<Notes>>
*7) Writing “1” to the BVAL bit is valid when the direction of the data packet is the sending direction (when data is
being written to the buffer memory). When the direction is the receiving direction, “BVAL=0” should be set.
*8) The BCLR bit and DTLN bit are valid for the buffer memory on the CPU side. Software should set “BCLR=1” or
refer DTLN bit after making sure that “FRDY=1”.
*9) Using the BCLR bit to clear the buffer should be done with the pipe invalid state by the pipe configuration
(“PID=NAK”).
*10) The FRDY bit requires an access cycle of at least 450 ns after the pipe has been selected.
CFIFO port SIE register [CFIFOSIE]
<Address: 22H>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TGL
SCLR SBUSY
0
-
0
-
0
-
0
?
Bit
Name
Function
S/W
H/W
Note
15 TGL
Access Right Switch
0: Invalid
1: Switches access right
R(0)/
W(1)
R/W(0) 3.4.2.3
14 SCLR
SIE Buffer Clear
0: Invalid
1: Clears buffer memory on SIE side
R(0)/
W(1)
R/W(0) 3.4.2.4
13 SBUSY
SIE Buffer Busy
0: SIE is not being accessed.
1: SIE is being accessed.
R
W
12-0 Nothing is placed here. These should be fixed at “0”.
<<Note>>
*11) The function of the TGL bit is to set the buffer memory on the SIE side to the CPU side. Set “PID=NAK” and
check the SBUSY bit to make sure the SIE is not accessing the buffer (“SBUSY=0”). Then write the TGL bit
(toggle operation). This bit is valid only for pipes for which the reception direction (reading from the buffer
memory) has been set.
*12) The function of the SCLR bit is to clear the buffer memory on the SIE side. Set “PID=NAK” and check the
SBUSY
bit to make sure the SIE is not accessing the buffer (“SBUSY=0”). Then clear the buffer. This bit is
valid only for pipes for which the sending direction (writing to the buffer memory) has been set.
相關(guān)PDF資料
PDF描述
M6XXLFXI OTHER CLOCK GENERATOR, QCC16
M300LFXIT 50 MHz, OTHER CLOCK GENERATOR, QCC16
M74HC00C1R HC/UH SERIES, QUAD 2-INPUT NAND GATE, PQCC20
M74HC157B1N HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16
M74HC158C1 HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PQCC20
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M66596WG#RB0Z 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0
M6668 制造商:Tamura Corporation of America 功能描述:
M66700P 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER
M66700WP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER
M66701P 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:DUAL HIGH-SPEED CCD CLOCK DRIVER
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*