
REVISION HISTORY
Rev.
Date
Description
Page
Summary
C-21
M32C/85 Group(M32C/85, M32C/85T) Hardware Manual
96
9.5.2.2 Entering Wait Mode Description modified
102
Figure 9.14 Status Transition Note 4 repleaced to note 5
103
9.6 System Clock Protection Function Description modified
Interrupt
111
Table 11.2 Relocatable Vector Table Fault Error deleted; Note 4 deleted
122
Figure 11.10 IFSR Register IFSR6 and IFSR7 bit functions changed
123
Figure 11.11 Key Input Interrupt Diagram modified
Watchdog Timer
129
Chapter description modified
Timer
160
Table 15.3 Timer Mode Specifications Write to Timer specification changed
162
Table 15.4 Event Counter Mode Specifications Write to Timer specification
changed
163
Table 15.5 Event Counter Mode Specifications Write to Timer specification
changed
168
Table 15.7 Pulse Width Modulation Mode Specifications Write to Timer
specification changed
169
Figure 15.13 TA0MR to TA4MR Registers Value after reset modified
174
Table 15.9 Timer Mode Specifications Write to Timer specification changed
175
Table 15.10 Event Counter Mode Specifications Write to Timer specification
changed
176
Figure 15.21 TB0MR to TB5MR Registers TCK1 bit name modified
178
Figure 15.22 TB0MR to TB5MR Registers Notes 1 and 2 modified
Serial I/O
194
Figure 17.1 UARTi Block Diagram Diagram modified
194
Figure 17.3 U0MR to U4MR Registers Value after reset modified
195
Figure 17.4 U0C0 to U4C0 Registers Note 1 modified
196
Figure 17.5 U0C1 to U4C1 Registers Note 2 modified
200
Figure 17.9 IFSR Register IFSR6 and IFSR7 bit functions changed
216
Table 17.13 Register Settings in I2C Mode SWC and ALS bit functions modified
223
17.3.6 SDA Input The IICM bit in the description modified to the IICM2 bit
224
Table 17.19 Special Mode 2 Specifications Transmit/Receive Control speci-
fication changed; Transmit Start Condision specification changed; Error Detec-
tion specification changed
225
Table 17.20 Register Settings in Special Mode 2 The IFSR6 register and its
function deleted
227
17.4.1.2 When Setting the DINC Bit to "0" (Master Mode) Description Modified
241
Figure 17.29 SIM Interface Operation Diagram modified
242
Figure 17.31 Parity Error Signal Output Timing (LSB First) Diagram modified