![](http://datasheet.mmic.net.cn/30000/M30855FHTGP_datasheet_2359399/M30855FHTGP_421.png)
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25. Flash Memory Version
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25.3 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands.
The user ROM area can be rewritten with the microcomputer mounted on a board without using a parallel
or serial programmer.
In CPU rewrite mode, only the user ROM area shown in Figure 25.1 can be rewritten. The boot ROM area
cannot be rewritten. The program and block erase commands are executed only for each block in the user
ROM area.
Erase-write (EW) mode 0 and erase-write mode 1 are provided as CPU rewrite mode. Table 25.3 lists
differences between EW mode 0 and EW mode 1.
Table 25.3 EW Mode 0 and EW Mode 1
NOTES:
_______
1. Do not generate an interrupt (except NMI interrupt) or a DMA transfer.
25.3.1 EW Mode 0
The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to "1" (CPU
rewrite mode enabled) and is ready to accept commands. EW mode 0 is selected by setting the FMR11
bit in the FMR1 register to "0". To set the FMR01 bit to "1", set to "1" after first writing "0".
The software commands control programming and erasing. The FMR0 register or the SRD register indi-
cates whether a program or erase operation is completed as expected or not.
25.3.2 EW Mode 1
EW mode 1 is selected by setting the FMR11 bit to "1" after the FMR01 bit is set to "1". (Both bits must
be set to "0" first before setting to "1".)
The FMR0 register indicates whether or not a program or erase operation has been completed as ex-
pected. The SRD register cannot be read in EW mode 1.
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