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17. Serial I/O (Special Function)
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17.7 Special Mode 5 (SIM Mode)
In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are
available and a low-level ("L") signal output can be provided from the TxDi pin (i=0 to 4) when a parity error
is detected.
Table 17.34 lists specifications of SIM mode. Table 17.35 lists register settings. Tables 17.36 to 17.38 list
pin settings.
Table 17.34 SIM Mode Specifications
Item
Specification
Transfer Data Format
Transfer data: 8-bit UART mode
One stop bit
In direct format
In inverse format
Parity:
Even
Parity:
Odd
Data logic:
Direct
Data logic:
Inverse
Transfer format:
LSB first
Transfer format:
MSB first
Transfer Clock
The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected):
fj/16(m+1)(1) fj = f1, f8, f2n(2) m : setting value of the UiBRG register, 0016 to FF16
Do not set the CKDIR bit to "1" (external clock selected)
Transmit/Receive Control
_______
The CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled)
Other Setting Items
The UiIRS bit in the UiC1 register is set to "1" (transmission completed)
Transmit Start Condition To start transmitting, the following requirements must be met:
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
Receive Start Condition To start receiving, the following requirements must be met:
- Set the RE bit in the UiC1 register to "1" (receive enable)
- Detect the start bit
Interrupt Request
While transmitting,
Generation Timing
-The UiIRS bit is set to "1" (transmission completed):
when data transmission from the UARTi transfer register is completed
While receiving,
when data is transferred from the UARTi receive register to the UiRB register (reception completed)
Error Detection
Overrun error(1)
This error occurs when the eighth bit of the next data is received before reading the
UiRB register
Flaming error
This error occurs when the number of the stop bit set is not detected
Parity error
This error occurs when the number of "1" in parity bit and character bits differs from
the number set
Error sum flag
The SUM bit is set to "1" when an overrun error, framing error or parity error occurs
NOTES:
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to
"1" (interrupt requested).
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).