![](http://datasheet.mmic.net.cn/30000/M30855FHTGP_datasheet_2359399/M30855FHTGP_219.png)
Page 196
4
9
4
f
o
5
0
2
,
1
0
.
l
u
J
3
0
.
1
.
v
e
R
3
0
1
0
-
7
3
0
B
9
0
J
E
R
17. Serial I/O
)
T
5
8
/
C
2
3
M
,
5
8
/
C
2
3
M
(
p
u
o
r
G
5
8
/
C
2
3
M
UARTi Transmit/Receive Control Register 1 (i=0 to 4)
Symbol
Address
After Reset
U0C1 to U4C1
036D16, 02ED16, 033D16, 032D16, 02FD16
0000 00102
RW
RI
UiIRS
UiRRM
UiLCH
TE
RE
TI
Transmit
Enable Bit
Transmit Buffer
Empty Flag
Receive
Enable Bit
Receive
Complete Flag
Clock-Divided
Synchronous Stop
Bit /
Error Signal
Output Enable
Bit(1)
SCLKSTPB
/UiERE
UARTi Transmit
Interrupt Cause
Select Bit
UARTi
Continuous
Receive Mode
Enable Bit
Data Logic
Select Bit(2)
0: Transmit disable
1: Transmit enable
0: Data in the UiTB register
1: No data in the UiTB register
0: Receive disable
1: Receive enable
0: No data in the UiRB register
1: Data in the UiRB register
0: No data in the UiTB register (TI = 1)
1: Transmission is completed (TXEPT = 1)
0: Disables continuous receive mode to be entered
1: Enables continuous receive mode to be entered
0: Not inversed
1: Inverse
Clock-divided synchronous stop bit (special mode 3)
0: Stops synchronizing
1: Starts synchronizing
Error signal output enable bit (special mode 5)
0: Not output
1: Output
Bit Name
Bit
Symbol
RO
RW
RO
RW
Function
NOTES:
1. Set the SCLKSTPB/UiERE bit after setting the SMD2 to SMD0 bits in the UiMR register.
2. The UiLCH bit setting is enabled when setting the SMD2 to SMD0 bits to "0012" (clock syncronous
serial I/O mode), "1002" (UART mode, 7-bit transfer data) or "1012" (UART mode, 8-bit transfer data).
Set the UiLCH bit to "0" when setting the SMD2 to SMD0 bits to"0102" (I2C mode) or "1102" (UART
mode, 9-bit transfer data).
b7
b6
b5
b4
b3
b2
b1
b0
UARTi Special Mode Register (i=0 to 4)
Symbol
Address
After Reset
U0SMR to U4SMR
036716, 02E716, 033716, 032716, 02F716
0016
RW
LSYN
ABSCS
ACSE
SSS
IICM
BBS
ABC
0: Except I2C mode
1: I2C mode
0: Update per bit
1: Update per byte
0: Stop condition detected
1: Start condition detected (Busy)
0: Disabled
1: Enabled
0: Not related to RxDi
1: Synchronized with RxDi
0: Rising edge of transfer clock
1: Timer Aj underflow(j=0 to 4)(2)
Bit Name
Bit
Symbol
I2C Mode Select Bit
Bus Busy Flag
NOTES:
1. The BBS bit is set to "0" by program. It is unchanged if set to "1".
2. UART0: timer A3 underflow signal, UART1: timer A4 underflow signal,
UART2: timer A0 underflow signal, UART3: timer A3 underflow signal,
UART4: timer A4 underflow signal.
3. Refer to notes for the SU1HIM bit in the UiSMR2 register.
Auto Clear Function Select
Bit for Transmit Enable Bit
SCLL Sync Output
Enable Bit
Arbitration Lost Detect
Flag Control Bit
Bus Conflict Detect
Sampling Clock Select Bit
Transmit Start
Condition Select Bit
0: No auto clear function
1: Auto clear at bus conflict
SCLKDIV
Clock Divide
Synchronous Bit
(Note 3)
RW
RW(1)
RW
Function
b7
b6
b5
b4
b3
b2
b1
b0
Figure 17.5 U0C1 to U4C1 Registers and U0SMR to U4SMR Registers