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e
R
3
0
1
0
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3
0
B
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9. Clock Generation Circuit
)
T
5
8
/
C
2
3
M
,
5
8
/
C
2
3
M
(
p
u
o
r
G
5
8
/
C
2
3
M
Figure 9.14 Status Transition
Main
Clock
Oscillation
Sub
Clock
Stop
On-Chip
Oscillator
Clock
Stop
PLL
Clock
Stop
CPU
Clock:
f(X
IN
)/8
CM07=0
MCD=08
16
CM21=0
CM05=0
CM04=0
PLC07=0
CM17=0
MCD=XX
16
(Note
1)
Main
Clock
Oscillation
Sub
Clock
Oscillation
On-Chip
Oscillator
Clock
Stop
PLL
Clock
Stop
CPU
clock
:f(X
IN
)
CM07=0
MCD=12
16
CM21=0
CM05=0
CM04=1
PLC07=0
CM17=0
CPU
clock:
f(X
IN
)/
n
(n
=2,3,4,6,8,10,12,14,16)
CM07=0
MCD=XX
16
CM21=0
CM05=0
CM04=1
PLC07=0
CM17=0
CM04=1
(Note
1)
Main
Clock
Oscillation
Sub
Clock
Stop
On-Chip
Oscillator
Clock
Oscillation
PLL
Clock
Stop
CPU
Clock:
On-Chip
Oscillator
Clock
/
n
(
n
=1,2,3,4,6,8,10,12,14,16)
CM07=0
MCD=XX
16
CM21=1
CM05=0
CM04=0
PLC07=0
CM17=0
CM21=1
(Note
1)
CM21=0
CM05=1
CM05=0
High-Speed
Mode
CM04=0
CM04=1
On-Chip
Oscillator
Mo
de
CM21=1
(Note
1)
CM21=0
CM04=0
CM04=1
CM04=0
CM04=1
Main
clock
stop
is
detected
when
CM20=1
(Note
5)
Low-Speed
Mode
CM07=0
(Note
1)
CM07=1
(Note
2)
PLC07=0
PLC07=1
Low-Speed
Mode
CM21=1
(Note
1)
CM21=0
Low-Power
Consumption
Mode
Low-Power
Consumption
Mode
CM05=1
CM05=0
CM05=1
CM05=0
CM07=0
CM07=1
(Note
2)
(Note
3)
After
reset,
Medium-Speed
Mode
(Divide-by-8)
(Note
4)
Main
clock
stop
is
detected
when
CM20=1
Medium-Speed
Mode
Main
Clock
Oscillation
Sub
Clock
Stop
On-Chip
Oscillator
Clock
Stop
PLL
Clock
Stop
CPU
clock:
f(X
IN
)
CM07=0
MCD=12
16
CM21=0
CM05=0
CM04=0
PLC07=0
CM17=0
CPU
clock:
f(X
IN
)/
n
(n
=2,3,4,6,8,10,12,14,16)
CM07=0
MCD=XX
16
CM21=0
CM05=0
CM04=0
PLC07=0
CM17=0
High-Speed
Mode
Medium-Speed
Mode
Main
Clock
Stop
Sub
Clock
Stop
On-Chip
Oscillator
Clock
Oscillation
PLL
Clock
Stop
CPU
Clock:
On-Chip
Oscil
lator
Clock
/
n
(
n
=1,2,3,4,6,8,10,12,14,16)
CM07=0
MCD=XX
16
CM21=1
CM05=1
CM04=0
PLC07=0
CM17=0
On-Chip
Oscillator
Lo
w-Power
Consumption
Mode
CM05=1
CM05=0
Main
Clock
Oscillation
Sub
Clock
Oscillation
On-Chip
Oscillator
Clock
Oscillation
PLL
Clock
Stop
CPU
Clock:
On-Chip
Oscil
lator
Clock
/
n
(
n
=1,2,3,4,6,8,10,12,14,16)
CM07=0
MCD=XX
16
CM21=1
CM05=0
CM04=1
PLC07=0
CM17=0
On-Chip
Oscillator
Mo
de
Main
Clock
Stop
Sub
Clock
Oscillation
On-Chip
Oscillator
Clock
Oscillation
PLL
Clock
Stop
CPU
Clock:
On-Chip
Oscillator
Clock
/
n
(
n
=1,2,3,4,6,8,10,12,14,16)
CM07=0
MCD=XX
16
CM21=1
CM05=1
CM04=1
PLC07=0
CM17=0
Main
Clock
Oscillation
Sub
Clock
Oscillation
On-Chip
Oscillator
Clock
Stop
PLL
Clock
Stop
CPU
clock:
f(X
CIN
)
CM07=1
CM21=0
CM05=0
CM04=1
PLC07=0
CM17=0
Main
Clock
Oscillation
Sub
Clock
Oscillation
On-Chip
Oscillator
Clock
Oscillation
PLL
Clock
Stop
CPU
Clock:
f(X
CIN
)
CM07=1
CM21=1
CM05=0
CM04=1
PLC07=0
CM17=0
Main
Clock
Stop
Sub
Clock
Oscillation
On-Chip
Oscillator
Clock
Oscillation
PLL
Clock
Stop
CPU
Clock:
f(X
CIN
)
CM07=1
MCD=08
16
CM21=1
CM05=1
CM04=1
PLC07=0
CM17=0
Main
Clock
Stop
Sub
Clock
Oscillation
On-Chip
Oscillator
Clock
Stop
PLL
Clock
Stop
CPU
Clock:
f(X
CIN
)
CM07=1
MCD=08
16
CM21=0
CM05=1
CM04=1
PLC07=0
CM17=0
Main
Clock
Oscillation
Sub
Clock
Oscillation
On-Chip
Oscillator
Clock
stop
PLL
Clock
Oscillation
CPU
clock:
f(X
IN
)
CM07=0
MCD=12
16
CM21=0
CM05=0
CM04=1
PLC07=1
CM17=0
CPU
clock:
f(X
IN
)/
n
(n
=2,3,4,6,8,10,12,14,16)
CM07=0
MCD=XX
16
CM21=0
CM05=0
CM04=1
PLC07=1
CM17=0
High-Speed
Mode
Medium-Speed
Mode
Main
Clock
Oscillation
Sub
Clock
Oscillation
On-Chip
Oscillator
Clock
Stop
PLL
Clock
Oscillation
CPU
clock:
f(X
PLL
)
CM07=0
MCD=12
16
CM21=0
CM05=0
CM04=1
PLC07=1
CM17=1
CPU
clock:
f(X
PLL
)/
n
(n
=2,3,4,6,8,10,12,14,16)
CM07=0
MCD=XX
16
CM21=0
CM05=0
CM04=1
PLC07=1
CM17=1
High-Speed
Mode
Medium-Speed
Mode
CM17=0
CM17=1
PLC07=0
PLC07=1
Main
Clock
Oscillation
Sub
Clock
Stop
On-Chip
Oscillator
Clock
Stop
PLL
Clock
Oscillation
CPU
clock:
f(X
PLL
)
CM07=0
MCD=12
16
CM21=0
CM05=0
CM04=0
PLC07=1
CM17=1
CPU
clock:
f(X
PLL
)/
n
(n
=2,3,4,6,8,10,12,14,16)
CM07=0
MCD=XX
16
CM21=0
CM05=0
CM04=0
PLC07=1
CM17=1
High-Speed
Mode
Medium-Speed
Mode
Main
Clock
Oscillation
Sub
Clock
Stop
On-Chip
Oscillator
Clock
Stop
PLL
Clock
Oscillation
CPU
clock:
f(X
IN
)
CM07=0
MCD=12
16
CM21=0
CM05=0
CM04=0
PLC07=1
CM17=0
CPU
clock:
f(X
IN
)/
n
(n
=2,3,4,6,8,10,12,14,16)
CM07=0
MCD=XX
16
CM21=0
CM05=0
CM04=0
PLC07=1
CM17=0
High-Speed
Mode
Medium-Speed
Mode
CM17=0
CM17=1
On-Chip
Oscillator
Lo
w-Power
Consumption
Mode
:
An
arrow
shows
mode
can
be
changed.
Do
not
chan
ge
mode
to
another
mode
when
no
arrow
is
shown.
MCD=XX
16
:Set
the
MCD
to
MCD0
bits
in
th
e
MCD
register
to
the
desired
division.
NOTES:
1.
Switch
the
clock
after
main
clock
oscillation
is
full
y
stabilized.
2.
Switch
the
clock
after
sub
clock
oscillation
is
full
y
stabilized.
3.
The
MCD4
to
MCD0
bits
in
th
e
MCD
register
are
set
to
"01000
2
"(devide-by-8
mode)
automatically
.
4.
The
CM05
bit
is
not
s
et
to
"1"
when
the
microcomputer
detects
a
main
clock
oscillation
stop
throu
gh
the
oscillation
stop
detection
circuit
.
5.
The
on-chip
oscillator
clock
runs
when
setting
the
PM22
bit
to
"1"
(
on-chip
oscillator
clock
as
watchdog
timer
count
source)
and
setting
the
PM27
and
PM26
bits
to
"10
2
"(
on-chip
oscillator
clock
),
even
if
the
CM21
bit
is
set
to
"0".
(Note
3)